模拟信号转数字信号的 vhdl转换程序

adc_interface.zip This zip file contains the following source code. VHDL SOURCE CODE: ----------------- top_level.vhd -- Top level VHDL file + adc_interface.vhd -- State machine implementation + shift16.vhd -- 16 bit shift register + shift8.vhd -- 8 bit shift register + upcnt5.vhd -- 5 bit up counter top_level.ucf -- Xilinx "User Constraints File". Used by Xilinx WebPACK software to assign pins VHDL TEST BENCHES: ------------------ top_level_tb.vhd -- Test top_level design adc_interface_tb.vhd -- Test adc_interface design