Quartus II 9.1使用教程操作笔记
Mew Project Vizard: Directory, Mane, Top-Level Entity Lpag. What is the working directory for thie prere? D: cpld-fpga What is the name of this project? Verilog 1 what is the name of the top-level design entity for this project? This name is case sensitive and must exactly match the entity name in the design file Use existing Project Settings Back Next Finish 取消 Her Project Lizard: Family Device Settings [page 3 of 5] x Select the family and device you want to target for compilation Device familt Show in available device list n Cyclone aca口e Devices: Pin count Target device Speed grade: Any C Auto device selected by the Fitter v Show advanced devices Specific de dected in a vailable devices list HardCopy compatible only Aγ ailable device Core. LEs Memo. PLL EP1C3T1O0C6 EPICST1O0C7 5R 10599041 2910 599041 EP1C3T1OOCH 15 599041 EP1C3T1007 15 2910599041 EPIC3T144A8 2910 59904 EP1C3T144C6 15 2910 EP1C3T144C 4 上F1C3T144C8 1.5 904 EPlC3T1447 乎u1 Companion device HardCopy V Limit DSP RAM to HardCopy device resources K Back I Hext>S Finish 取 H Quartus II- D:/cpld fpga/verilog_ 1- verilog_1 File)Edit View Project Assi grments Processing Tools Window Hel Ctrltl d verilog_1 踩华 Ctrlt0 CLose CtrltFa Tew Project置izrd 属卩 en Project trlt, invert MA+P士 Project t lose Project Trite 点 Save Current Report Section As File Properties Create Update Export overt Programming files Page Setup a Print Preview sPr Ctrl Recent files Recent Proiects AlttF4 Flanner et SOPC Builder System Design files AHDL File Block diagram/ schematic file EDIF File State machine file Systemverilog hdl file Tcl Script Fi Verilog HDl file护 HDL FIle 口- Memory file: Hexadecimal [ntel-Format] file Memory Initialization file a verification Debugging files rces and Probes file Logic Analyzer Interface file Signal ap ll logic analyzer file Vector waveform file -.Other Files AHDL Include file Block Symbol Fi Chain description File Synopsys Design Constraints File Text file OK Q4 Quartus II- D: /cpld fpga/verilog verLo [ ⊥a g1. 回例「 双多 Project Navigator a abc verilog.ye Enti 公 Cyclone:EBC3r144 1 Module verilog 1(input clk, output reg q); A always ((posedge clk) egin =~q 6 endmodule △画 另存为 保存在 cpld- tpga Flow: Compilation db Task区 我最近的文档 日 Compile Desig 岛 桌面 Par tit 我的文档 里v etl 我的电脑 m Type Message 网上邻居 立件名c):r10 保存) Processing A Extra Into AInf入 保存类型〕 1 O= HDL File〔 t verily 取消 stell h Message t a. v Add file to current project L Quartus II- D:/cpld fpga/verilog_1 verilog_ 1- [Compilation Report -Flo Summaryl File Edit View Project( At ats ) Processing Tools Mindow Help 日昌唱 Device Project Navigator 卫i Itl tT Oy Timing Anaysis Settings Compilation Report-Flow Summary △1:y0 Tool Settings Settings 匚tr1+ hitt十E Classic Timing Analyzer Wizard Assignment Editor CtrltShifttA F1wSt江t1雪 Successful -t tx1+Shi￡t十 Quartus工工 1 Build 222 Revision lame verilog 1 Remove Assignment Top-level Entity Name Trer11oe Demote Assignment Family Cyclone BackAnnotate Assi grments EP1C3T144C8 Tasks port Assignment Timing Models Final Flow: Compilati Export Assignments Met timing requirements Yes Total logic elements 2,10(< Task y Assignment (Time)Groups Total pins 2了104(2器 Compile design Timing Closure floorpl an Total virtual pins Total memory b 059,904〔0 edit s A Logi cLock Regions Window Alt+L Total plls 0}1〔0%〕 E View Re.E2 Design Partitions Window Alto Analys Partiti e Message a warning: The Reserve All Unused Pins setting has not been specifiec a Warning: Found pins functioning as undefined clocks and or memory e Settings- verilog 1 tegory General Device Device and Pin Options Select the family and device you want to target for compilation Pin Placement g Error Detection CEC Capacitive Loading Board Trace Model I/0Timing Operating setti Device family oW in available devices list Configuration Programming File Unused pins compilatiOn Process setting +· EDA Tool setting Family: Cyclone de'vice-Wide options for reserving sed pins on the device. To reserve Synthesis settings Pin count:Any individual dual-purpose configuration pins, ao to the dual- purpose pins tab Fitter Settings reserve other pins individually, use the As signment Editor + Timing Analysis Setting peed gr Assembler arget device 厂5 how adv anced devices Design Assistant C Auto device selected by the Fitter alTp‖ Logic analy 厂 HardCopy compatible only C Specific device selected in Available devices'list Logic analyzer Interface +· Simulator Setting C Other: n/a Device and Pin options PowerPlay Power Analyzer Settings SSN Analyzer Available devicet ↓a I Core . LE: Memor. PLL EP1C3T 1OOC6 15 2010 5g9041 EP1C3T100C 1 2910599041 Description: P1C3T1000 2910 53941 Reserves all unused pins on the target device in one of 5 states: as inputs that are EP1C3T1007 91059904 tri-stated, as outputs that drive ground as outputs that drive an unspecified signal, EF1C31448 as input tri-stated with bus- hold, or as input tri-stated with weak pull-up EPIC3T1446 599T41 EP1C3T144c7 日 13T144C8 Migration compatibility Comparion device Migration Devices HardCopy. O migration devices selected F Limit DSP& RAM to HardCopy device resource 确定 取消 Cancel Quartus II D:/cpld fpga/verilog 1- verilog 1- [aveforl wf] File Edit View Project i Assignment ocessing Tools Window Help Pi LS Project Navigator Entity a Timing analysis Settings I Compilation Report- Flow Sumr cter t ime bar 175 Pointer Inter L i td verilog 1 E Settings t1+Shi￡t+E 1 10.0ns Yalue at Tame CI . 1ng er坐 izard 17.6ns A三 ignment ed CtrltShifttA Pin Planner 匚tx1+ Shi. 已mF 1eTt三 Demote Assignment 4 m f Back-Annotate Assignments △ Hierarchy Files中Degn Import Assignments ort Assignments ssignment (Tim 中s Compilati on liLI Floorpl Task圖 nindo Compile i L nalysis g s 品 esi红 Partitions wind Attn edit sett