STM8S001官方手册

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STM8S001官方手册STM8S001官方手册STM8S001官方手册STM8S001官方手册
STM8S001J3 Contents 6.2.3 CPU/SWIM/debug module/interrupt controller registers 33 Interrupt vector mapping 35 Option bytes∴…∴…∴∴∴.….… 36 8.1 Alternate function remapping bits 38 Electrical characteristics 9.1 Parameter conditions 9.1.1 Minimum and maximum values 39 9.1.2 Typical values 39 9.1.3 Typical curves 39 9.1.4 Loading capacitor 9.1.5 Pin input voltage 39 9.2 Absolute maximum ratings 40 9.3 Operating conditions 42 9.3.1 VCAP external capacitor 44 9.3.2 Supply current characteristics .44 9.3.3 Extemal clock sources and timing characteristics 9.3.4 Internal clock sources and timing characteristics 53 9.3.5 Memory characteristics ,,,,56 9.3.6 1/0 port pin characteristics 9.3.7 SPI serial peripheral interface 65 9.3.8 2C interface characteristics 9.39 10-bit adc characteristics .70 9.3. 10 EMC characteristics ..,,,73 Package information 76 10.1 So8N package information 76 10.2 Thermal characteristics .·.·· 78 10.2.1 Reference document 10.2.2 Selecting the product temperature range Ordering information n,,∴,80 12 STM8 development tools . ...................................81 12.1 Emulation and in-circuit debugging tools 8 DocID030584 ReV 2 3/84 Contents STM8S001J3 12.2 Software tools 82 12.2.1 STM8 toolset .82 12.2.2 C and assembly toolchains 82 12.3 Programming tools 82 13 Revision history ......................83 4/84 DocID030584 ReV 2 STM8S001J3 List of tables List of tables Table 1 STM8S001J3 features Table 2. Peripheral clock gating bit assignments in CLK PCKENR 1/2 registers ..15 Table 3 TIM timer features 18 Table 4. Legend/abbreviations for STM8S001J3 pin description tables 0 Table 5 STM8S001J3 pin description Table 6. Flash, Data EEPROM and rAM boundary addresses .,,,,25 Table 7. 1/0 port hardware register map 25 Table 8. General hardware register map .27 Table 9. CPU/SWIM/debug module/interrupt controller registers 33 Table 10. Interrupt mapping 35 Table 11. Option bytes 36 Table 12. Option byte description Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices Table 14. Voltage characteristics Table 15. Current characteristics 4 Table 16, thermal characteristics Table 17. General operating conditions 42 Table 18. Operating conditions at power-up/power-down Table 19. Total current consumption with code execution in run mode at VDD=5V ,44 Table 20. Total current consumption with code execution in run mode at VDD =3.3V .45 Table 21. Total current consumption in wait mode at VoD=5V 46 Table 22. Total current consumption in wait mode at VDD=3.3V Table 23. Total current consumption in active halt mode at Vod=5v Table 24. Total current consumption in active halt mode at VDD =3.3V Table 25. Total current consumption in halt mode at VoD =5 V 48 Table 26. Total current consumption in halt mode at VDD =3.3V ,,,,48 Table 27. Wakeup times .48 Table 28. Total current consumption and timing in forced reset state 49 Table 29. Peripheral current consumption 49 Table 30. hse user external clock characteristics 53 Table 31. hsl oscillator characteristics 54 Table 32. lsi oscillator characteristics 54 Table 33. RAM and hardware registers 6 Table 34. Flash program memory and data EEPROM ..,,.56 Table 35. l /o static characteristics .57 Table 36. Output driving current (standard ports 59 Table 37. Output driving current(true open drain ports 59 Table 38. Output driving current(high sink ports) ..60 Table 39. sP characteristics 65 Table 40. 2c characteristics 68 Table 41. Adc characteristics 70 Table 42. ADC accuracy with Rain <10 kQ, Vdp=5v .70 Table 43. ADC accuracy with RAiN <10 kQ2 RAIN, VDD=3.3V Table 44. ems data 73 Table 45. emi data 74 Table 46. ESD absolute maximum ratings 74 Table 47. Electrical sensitivities 75 Table 48. SO8N-8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, DocID030584 ReV 2 5/84 List of tables STM8S001J3 package mechanical data .76 Table 49. Thermal characteristics .79 Table 50. Document revision history 8 6/84 DocID030584 ReV 2 STM8S001J3 List of figures List of figures Figure 1. STM8S001J3 block diagram 10 Figure 2. Flash memory organization 13 Figure 3. STM8S001J3 SO8N pinout :.:::::: ...20 Fi gure 4 Memory map 24 Figure 5. Pin loading conditions Figure 6. Pin input voltage Figure 7. fcPUmax versus Vpp 42 Figure 8. External capacitor CeXt 44 Figure 9. Typ. IDD(RUN) VS VDD, HSE user external clock, fcPu=16 MHz Figure 10. Typ. IDD(RUN) VS CPU, HSE user external ClocK,VDD-5VNz 50 50 Figure 11. Typ. IDD(RUN)VS VDD, HSI RC OSC, cPU=16 MHZ 5 Figure 12. Typ. DD(WFI) VS VDD HSE user external clock, TCPU=16 MHZ 5 Figure 13. Typ. DD(WFIVS fcPU, HSE user external clock, VDD=5V ..52 Figure 14. Typ. DD(WFI) VS VDD, HSRC oSC, fcPU=16 MHz 52 Figure 15. HSE external clock source Figure16. Typical HSI frequency variation Vs VDp at4 temperatures.….………∴∴.54 Figure 17. Typical LSI frequency variation VS VDD@ 4 temperatures ..55 Figure 18. Typical Vil and VIH vs Vdp@ 4 temperatures 58 Figure 19. Typical pull-up resistance Vs VDp a 4 temperatures 8 Figure 20. Typical pull-up current VS VDD@4 temperatures Figure 21. Typ. VOL Q VDD=5V(standard ports) ..,,,60 Figure 22. Typ. VOL Q VDD =3.3 V(standard ports) Figure 23. Typ. VOL Q VDD=5V(true open drain ports) Figure 24. Typ. VOL O VDD=3.3 V(true open drain ports) 62 Figure 25. Typ. Vol VDD =5V(high sink ports) 62 Figure 26. Typ. VOL O VDD =3.3V(high sink ports) ..63 Figure 27. Typ. VDD -VOH O VDD=5V(standard ports) Figure 29. Typ. VDD-VOH CKOD=3. 3 Figure 28. Typ. VDD-VOH@ VD V (standard ports 64 dp=5V(high sink ports Figure 30. Typ. VpD- NOH VDD=3. 3 V(high sink ports) 64 65 Figure 31. SPI timing diagram-slave mode and CPHA=0 .66 Figure 32. SPI timing diagram -slave mode and CPHA=1(1) Figure 33. SPI timing diagram-master mode ...67 Figure 34. Typical application with 12C bus and timing diagram .69 Figure 35. Adc accuracy characteristics 72 Figure 36. Typical application with ADC 72 Figure 37. SO8N-8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline. 76 Figure 38. SO8N-8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint Figure 39. SO8N-8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, marking example 78 Figure 40. STM8S001J3 ordering information scheme (1) ......80 DocID030584 ReV 2 7/84 Introduction STM8S001J3 Introduction This datasheet contains the description of the STM8S001J3 features, pinout, electrical characteristics, mechanical data and ordering information For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the sTM8s and sTM8A microcontroller families reference manual(RMo016) For information on programming, erasing and protection of the internal Flash memory please refer to the PMo051(How to program STM8S and STM8A Flash program memory and data EEPROM) For information on the debug and SWiM (single wire interface module)refer to the STM8 SWIM communication protocol and debug module user manual (UM0470) For information on the STM8 core, please refer to the stM8 CPU programming manual (PM044) 8/84 DocID030584 ReV 2 STM8S001J3 Description 2 Description The STM8S001J3 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. it is referred to as low-density device in the sTm8s microcontroller family reference manual(RM0016) The stM8s001J3 device provides the following benefits: performance, robustness and reduced system cost Device performance and robustness are ensured by true data eeProm supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog and brown-out reset Full documentation is offered as well as a wide choice of development tools Table 1. stM8S001J3 features Features STM8S001J3 Pin count 8 Max number of GPlOs((/O) External interrupt pins 5 Timer CaPCom channels 3 Timer complementary outputs AD converter channels 3 High-sink I/Os 4 LOw-density Flash program memory (byte) 8 K RAM (byte) 1 K True data eEPRoM(byte) 128 (1) Multi purpose timer(TIM1), SPl unidirectional, I2C, UART, Window wdg Peripheral set independent WDG, ADC, PWM timer(TIM2),8-bit timer (TM4) 1. Without read-while-write capability DocID030584 ReV 2 9/84 Block diagram STM8S001J3 3 Block diagram Figure 1. STM8S001J3 block diagram Ext Clock input Reset block Clock controller 1-16 MHz RC int. 16 MHz Detector ORBOR RC int. 128 kl Clock to peripherals and Window WDG STM8 core Kr> > Independent WDG 8 kbyte Iterface gram Flash kn data E PROM 400 Kbit/s 12C 1 Kbyte RAM Up to 2 Mue→+cm CAPCPOM channels 16-bit general Up to 3 LIN maste UART1 purpose time CAPCPOM (TIM2) channels p to 3 ADC 1 channels K少 8-bit basic timer (TIM4) NU timer 0/84 DocID030584 ReV 2

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