IECON'O1: The 27th Annual Conference of the IEEE Industrial Electronics Society
A
New On-line Dead-Time Compensation Method
Based on
Time
Delay
Control
Hyun-Soo
Kim,
Hag-Wone
Kim,
and Myung-Joong Youn
Department of Electrical Engineering and Computer Science,
Korea Advanced Institute of Science and Technology,
373-1 Kusong-Dong, Yusong-Gu, Taejon 305-701, Korea.
ABSTRACT
-
In this paper, an on-line dead-time
compensation method based on a time delay control
approach is presented. The disturbance voltages caused by
the dead time are estimated in an on-line manner by the time
delay control without any additional circuits and off-line
experimental measurements. And the estimated disturbance
voltages are fed to voltage references in order to compensate
the dead-time effects. The proposed method is applied to a
PM synchronous motor drive system and implemented by
using software
of
a digital signal processor
(DSP)
TMS320C31. Experiments are carried out for this system
and the results well demonstrate the effectiveness of the
proposed method.
I.
INTRODUCTION
In recent years, due to the development of high speed
switching devices such as power transistors and insulated
gate bipolar transistors
(IG
BT's),
pulse width modulated
(PWM) voltage source inverters
(VSI's)
are widely used
in adjustable speed motor drives.
In
a PWM VSI, because of a dead time which is
inevitable to prevent the simultaneous conduction of two
switching devices in each leg
of
the inverter,
a
distortion
of the inverter output voltage, which is called as
'dead-
time
effects',
arises. The distortion of the inverter output
voltage affects machine currents
so
that a phase current
distortion, torque pulsations and degradations of control
performance are caused [3]-[ lo].
In order to overcome the above problem due to the dead
time, various approaches are presented. The one is based
on modified PWM gate signals, where these signals are
made from either hardware correction circuits [3]-[5]
or
a
software correction circuit in [6]. The other is based on a
feedforward approach, where the compensating voltages
obtained from current polarities and prescribed values are
fed to the voltage references [7]-[
101.
Non-ideal switching
characteristics of the power device such as finite switching
times and voltage drops of switching devices are also
considered in some approaches[8][9].
However, most previous approaches are only
implemented by off-line manners. It is difficult to
compensate the dead-time effects perfectly by off-line
manners since the switching times and voltage drops
of
the power devices are varied with operating conditions
such as the DC link voltage, phase currents, operating
frequency, and motor speed
[IO].
Although an on-line
method is proposed in [IO], the method needs additional
hardware circuits such as
a
zero crossing detector and a
r
Fig.
I.
Practical switching pattern. (a) ideal gate signal patterns.
(b)
practical gate signal pattern with consideration
of
dead time. (c) actual
output
voltage with consideration
of
dead time and switching time for
i.,
>O
.
(d)
actual output voltage with considcration
of
dead time and
switching time for
i,,
<
0
.
time counter together with off-line experimental
measurements to set up a look-up table.
Thus, in this paper, a new on-line dead-time
compensation method is proposed. The proposed method
does not need any additional hardware circuits and off-line
experimental measurements. The disturbance voltages
caused by the dead time are estimated by a time delay
control approach and fed to voltage references in order to
compensate the dead-time effects. The proposed method is
applied to a PM synchronous motor drive system and
implemented in a digital manner using a digital signal
processor (DSP) TMS320C3
1.
The experiments are carried
out for this system to show the effectiveness of the
proposed method.
11.
ANALYSIS
OF
DEAD-TIME EFFECT
Since a switching device has a finite switching time, a
dead time should be considered in the PWM gate signals in
order to prevent the simultaneous conduction
of
two
switching devices in each leg of the inverter. In other
words, a top switching
of
one phase leg should be turned
off before a bottom switching the leg is turned on and vice
0-7803-7108-9/01/$10.00 (C)2001
IEEE
1184
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