DDI0403C_arm_architecture_v7m_reference_manual_errata_markup_2_0

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ARMv7-M Architecture Reference Manual ARMv7-M Architecture Reference Manual
This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out above In this document, where the term ARM is used to refer to the company it means "ARM or any of its subsidiaries as appropriate Note The term ARM is also used to refer to versions of the aRM architecture, for example armv6 refers to version 6 of the aRM architecture. The context makes it clear when the term is used in this way Note This errata pdF is regenerated from the source files of issue C of this document, but The pseudocode examples, that are inserted into the document have been updated. Significant changes in the pseudocode are highlighted Pages ii and iii of the Pdf have been replaced, by an edit to the pdf, to include an updated Proprietary With these exceptions, this pdf corresponds to the released pdF of issue C of the document, with errata indicated by markups to the PDF In the revised pseudocode, the function BadReg(x)is replaced by a new construct, x IN [13, 15], that can be used in other contexts. This is a format change only ARM DDI 0403C errata Copyright o 2006-2009 ARM Limited. All rights reserved D071709 Non-Confidential Restricted Access Copyright C 2006-2008 ARM Limited. All rights reserved. ARM DDI 0403C Non-Confidentia/ Restricted Access Contents ARMV7-M Architecture Reference manual Preface about this manual X Using this manua B国面面面面面面B国 Conventions ∴XXl Further reading… XXIII Feedback Part A Application Level Architecture Chapter a1 Introduction A1.1 The ARM architecture -M profile A1-2 Chapter A2 Application Level Programmers'Model A2. 1 About the application level programmers' model A22 A2.2 ARM core data types and arithmetic A2-3 A2.3 Registers and execution state A2-11 A2.4 Exceptions faults and interrupts................... A2-15 A2.5 Coprocessor support A2-16 Chapter A3 ARM Architecture Memory Model A3.1 Address space .A3-2 ARM DDI 0403C Copyright@ 2006-2008 ARM Limited. All rights reserved. Restricted Access Non-Confidential A3.2 Alignment support A3-3 A3.3 Endian support A3-5 A3. 4 Synchronization and semaphores A3-8 A3. 5 Memory types and attributes and the memory order model .... A3-18 A3.6 Access rights A3-28 A3.7 Memory access order…… 面面面面面B A330 A3.8 Caches and memory hierarchy ∴A3-38 Chapter A4 The arMv7-M Instruction set A4. 1 About the instruction set .““ A4-2 A42 Unified Assembler Language .A4-4 A4.3 Branch instructions A4-7 A4.4 Data-processing instructions A4-8 A4.5 Status register access instructions A4-15 A4. 6 Load and store instructions A4-16 A4.7 Load/store multiple instructions 面面面面 A4-19 A4.8 miscellaneous instructions A4-20 A4.9 Exception- generating instructions………… A4-2 A4.10 Coprocessor instructions A4-22 Chapter A5 Thumb Instruction Set Encoding A5.1 Thumb instruction set encoding ..A5-2 A5.2 16-bit Thumb instruction encoding A5-5 A5. 3 32-bit Thumb instruction encoding A5-13 Chapter A6 Thumb Instruction Details A6. 1 Format of instruction descriptions A6-2 A6.2 Standard assembler syntax fields A6-7 A6.3 Conditional execution A6-8 A6.4 Shifts applied to a register ∴A6-12 A6.5 Memory accesses A6-15 A6 6 Hint Instructions 6-16 A6.7 Alphabetical list of ARMv7-M Thumb instructions 6-17 Part B System Level Architecture Chapter B1 System Level Programmers'Model B1.1 Introduction to the system level B1-2 B1.2 ARMV7-M: a memory mapped architecture B13 B1.3 System level operation and terminology overview B1-4 B1.4 Registers B1-8 B1.5 Exception model B1-14 Chapter B2 System Memory Model B2.1 Introduction B2-2 Copyright C 2006-2008 ARM Limited. All rights reserved. ARM DDI 0403C Non-Confidentia/ Restricted Access Contents B2.2 Pseudocode details of general memory system operations B2-3 Chapter B3 System Address Map B3. 1 The system address map B3-2 B3.2 System Control Space(SCS) B3-6 B3.3 System timer- Sys Tick B3-24 B3. 4 Nested Vectored Interrupt Controller(NVIC) B3-28 B3.5 Protected Memory System Architecture( PMSAV7)…………………B3-35 Chapter b4 ARMV7-M System Instructions B4.1 Alphabetical list of ARMv7-M system instructions B4-2 Part c Debug Architecture Chapter C1 ARMV7-M Debug C11 Introduction to debug C1-2 C1.2 The Debug Access Port (DAP) C1-4 C1.3 Overview of the ARMv7-M debug features C1-8 C1. 4 Debug and rese C1-13 C1.5 Debug event behavior C1-14 C1.6 Debug register support in the SCS C1-19 C1.7 Instrumentation Trace Macroce(TM) support….….…………c1-27 C1.8 Data Watchpoint and Trace(DWT) support C133 C1. 9 Embedded Trace(ETM) support C1-56 C1.10 Trace Port Interface Unit (TPlU) C157 C1.11 Flash Patch and Breakpoint(FPB) support C1-61 Appendix A CPUID A.1 re Feature id Regis AppxA-2 A2 Processor Feature register (ID_PFRO AppxA-4 A3 Processor Feature register1(ID_PFR1) AppxA-5 A 4 Debug Features register(ID_DFRO … Appa-6 A.5 Auxiliary Features register(D_AFRO)……… AppA-7 A6 Memory Model Feature registers AppxA-8 A7 Instruction Set Attribute registers - background information.. AppxA-10 A.8 Instruction Set Attribute registers -details AppxA-12 Appendix B ARMv7-M infrastructure IDs Appendixc Legacy Instruction Mnemonics Thumb instruction mnemonics AppX C-2 C 2 Pre-UAL pseudo-instruction NOP appXC-6 ARM DDI 0403C Copyright@ 2006-2008 ARM Limited. All rights reserved. Restricted Access Non-Confidential Contents Appendix d Deprecated Features in ARMV7-M Appendix e Debug ITM and dWT packet protocol E.1 Packet Types AppxE-2 E2 DWT packet formats 1面面 …… AppE8 Appendix F ARMv7-R differences F.1 Endian support AppxF-2 F2 Application level support AppxF-3 F.3 System level support……… AppxF-4 F 4 Debug support AppXF-5 Appendix g Pseudocode definition G.1 Instruction encoding diagrams and pseudocode AppX G-2 G2 Limitations ot ps pseudocode AppX G-4 G3 Data Types AppxG-5 G4 Expressions AppXG-9 G5 Operators and built-in functions Appx G-11 G6 Statements and program structure … AppXG-17 G.7 Miscellaneous helper procedures and functions……… AppXG22 Appendix H Pseudocode Index H.1 Pseudocode operators and keywords……………….…….. AppXH-2 H 2 Pseudocode functions and procedures AppxH-5 Appendix I Register Index .1 ARM core registers Appx -2 .2 Memory mapped system registers………….…….….,…,….……Appx|-3 .3 Memory mapped debug registers AppxI-5 Glossary Copyright C 2006-2008 ARM Limited. All rights reserved ARM DDI 0403C Non-Confidentia/ Restricted Access List of tables ARMV7-M Architecture Reference manual Change History Table a3-1 Little-endian byte format A3-5 Table A3-2 Big-endian byte format A3-5 Table A3-3 Little-endian memory system A3-6 Table A3-4 Big-endian memory system ∴A3-6 Table a3-5 Load-store and element size association A3-7 Table a3-6 Effect of Exclusive instructions and write operations on local monitor A3-10 Table a3-7 Effect of load/store operations on global monitor for processor(n) A3-14 Table a3-8 Memory attribute summary A3-19 Table a4-1 Branch instructions 面面B A4-7 Table a4-2 Standard data-processing instructions A49 Table a4-3 Shift instructions A4-10 Table a4-4 General multiply instructions A4-11 Table a4-5 Signed multiply instructions A4-11 Table a4-6 Unsigned multiply instructions A4-11 Table a4-7 Core saturating instructions A4-12 Table a4-8 acking and unpacking instructions A4-13 Table a4-9 Miscellaneous data-processing instructions A4-14 Table a4-10 Load and store instructions A4-16 Table a4-11 Load/ store multiple instructions…… .A4-19 Table a4-12 Miscellaneous instructions A4-20 Table a5-1 16-bit Thumb instruction encoding ∴A5-5 Table a5-2 16-bit shift(immediate), add, subtract, move and compare encoding A5-6 ARM DDI 0403C Copyright@ 2006-2008 ARM Limited. All rights reserved. Restricted Access Non-Confidential ist of tables Table A5-3 6-bit data processing instructions ∴A5-7 Table a5-4 Special data instructions and branch and exchange A5-8 Table A5-5 16-bit Load/store instructions .A5-9 Table A5-6 Miscellaneous 16-bit instructions .A5-10 Table a5-7 If-Then and hint instructions .A5-11 Table a5-8 Branch and supervisor call instructions 面面面面 A5-12 Table A5-9 32 bit Thumb encoding… A5-13 Table A5-10 32-bit modified immediate data processing instructions A5-14 Table A5-11 Encoding of modified immediates in thumb data- processing instructions A5-15 Table A5-12 32-bit unmodified immediate data processing instructions .A5-17 Table a5-13 Branches and miscellaneous control instructions A5-18 Table a5-14 Change processor state and hint instructions A5-19 Table A5-15 Miscellaneous control instructions A5-19 Table A5-16 Load/store multiple instructions .A5-20 Table A5-17 Load/store dual or exclusive, table branch A5-21 Table A5-18 Load word A5-22 Table A5-19 Load halfword A5-23 Table a5-20 Load byte, preload A5-24 Table A5-21 Store single data item A5-25 Table A5-22 Data-processing(shifted register) A5-26 Table A5-23 Move register and immediate shifts ..A5-27 Table a5-24 Data processing(register) A5-28 Table A5-25 Miscellaneous operations A5-29 Table a5-26 Multiply, and multiply accumulate operations………….… ∴A5-30 Table A5-27 Long multiply, long multiply accumulate, and divide operations A5-31 Table A5-28 Coprocessor instructions ..A5-32 Table a6-1 Condition codes .A6-8 Table A6-2 Effect of it execution state bits 6-11 Table A6-3 Determination of mask field A6-79 Table A6-4 MOV(shift, register shift) equivalences) A6-152 Table b1-1 Mode, privilege and stack relationshi B14 Table b1-2 The xP SR register layout B19 Table b1-3 ICit bit allocation in the ePsr B1-10 Table b1-4 The special-purpose mask registers B1-10 Table B1-5 EXception numbers B1-16 Table b1-6 Vector table format B1-16 Table b1 -7 Priority grouping B1-18 Table b1-8 Exception return behavior B1-26 Table b1-9 List of supported faults B1-40 Table B1-10 Behavior of faults which occur during NM or HardFault execution .... B1-45 Table b3-1 ARMV7-M address map B3-3 Table B3-2 SCS address space regions B3-6 Table B3-3 System control and ID registers∴… B3-7 Table b3-4 Auxiliary Control Register-(OXE00OE008) .B3-9 Table b3-5 CPUID Base Register-(CPU|D,OXE000ED00)………………………B310 Table b3-6 Interrupt Control and State Register-(0E000ED04)……… B3-12 Table b3-7 Vector Table Offset Register-(OXE00OEDO8 .B3-13 Copyright C 2006-2008 ARM Limited. All rights reserved ARM DDI 0403C Non-Confidentia/ Restricted Access

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