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101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Nios II Processor Reference Handbook

NII5V1-6.0

Altera Corporation iii

Contents

Chapter Revision Dates .......................................................................... vii

About This Handbook .............................................................................. ix

Introduction ............................................................................................................................................... ix

Assumptions about the Reader ..................................................................................................... 1–ix

How to Find Further Information ........................................................................................................... x

How to Contact Altera .............................................................................................................................. x

Typographical Conventions .................................................................................................................... xi

Section I. Nios II Processor

Revision History .................................................................................................................................... I–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Nios II Processor System Basics ..................................................................................................... 1–1

Getting Started with the Nios II Processor ................................................................................... 1–2

Customizing Nios II Processor Designs ........................................................................................ 1–3

Configurable Soft-Core Processor Concepts ...................................................................................... 1–3

Configurable Soft-Core Processor .................................................................................................. 1–4

Flexible Peripheral Set & Address Map ........................................................................................ 1–4

Custom Instructions ......................................................................................................................... 1–5

Automated System Generation ...................................................................................................... 1–5

Chapter 2. Processor Architecture

Introduction ............................................................................................................................................ 2–1

Processor Implementation .................................................................................................................... 2–2

Register File ............................................................................................................................................ 2–3

Arithmetic Logic Unit ........................................................................................................................... 2–3

Unimplemented Instructions .......................................................................................................... 2–4

Custom Instructions ......................................................................................................................... 2–4

Floating Point Instructions .............................................................................................................. 2–4

Reset Signals ........................................................................................................................................... 2–5

Exception & Interrupt Controller ........................................................................................................ 2–6

Exception Controller ........................................................................................................................ 2–6

Integral Interrupt Controller ........................................................................................................... 2–6

.................................................................................................................................................................. 2–6

Memory & I/O Organization .............................................................................................................. 2–6

Instruction & Data Buses ................................................................................................................. 2–8

iv Altera Corporation

Nios II Processor Reference Handbook

Contents

Cache Memory ................................................................................................................................ 2–10

Tightly Coupled Memory ............................................................................................................. 2–12

Address Map ................................................................................................................................... 2–13

JTAG Debug Module .......................................................................................................................... 2–13

JTAG Target Connection ............................................................................................................... 2–14

Download & Execute Software .................................................................................................... 2–14

Software Breakpoints ..................................................................................................................... 2–14

Hardware Breakpoints .................................................................................................................. 2–14

Hardware Triggers ......................................................................................................................... 2–15

Trace Capture .................................................................................................................................. 2–16

Chapter 3. Programming Model

Introduction ............................................................................................................................................ 3–1

General-Purpose Registers ................................................................................................................... 3–1

Control Registers ................................................................................................................................... 3–2

Operating Modes ................................................................................................................................... 3–4

Supervisor Mode .............................................................................................................................. 3–5

User Mode ......................................................................................................................................... 3–5

Debug Mode ...................................................................................................................................... 3–6

Changing Modes .............................................................................................................................. 3–6

Exception Processing ............................................................................................................................. 3–8

Exception Types ................................................................................................................................ 3–8

Determining the Cause of Exceptions ......................................................................................... 3–11

Nested Exceptions .......................................................................................................................... 3–13

Returning from an Exception ...................................................................................................... 3–13

Break Processing .................................................................................................................................. 3–14

Processing a Break .......................................................................................................................... 3–14

Returning from a Break ................................................................................................................. 3–14

Register Usage ................................................................................................................................ 3–15

Memory & Peripheral Access ............................................................................................................ 3–15

Addressing Modes ......................................................................................................................... 3–15

Cache Memory ................................................................................................................................ 3–16

Processor Reset State ........................................................................................................................... 3–16

Instruction Set Categories ................................................................................................................... 3–17

Data Transfer Instructions ............................................................................................................ 3–17

Arithmetic & Logical Instructions ...............................................................................................3–19

Move Instructions ........................................................................................................................... 3–20

Comparison Instructions ............................................................................................................... 3–20

Shift & Rotate Instructions ............................................................................................................ 3–21

Program Control Instructions ....................................................................................................... 3–22

Other Control Instructions ............................................................................................................ 3–23

Custom Instructions ....................................................................................................................... 3–23

No-Operation Instruction ............................................................................................................. 3–23

Potential Unimplemented Instructions ....................................................................................... 3–24

Chapter 4. Implementing the Nios II Processor in SOPC Builder

Introduction ............................................................................................................................................ 4–1

Altera Corporation v

Nios II Processor Reference Handbook

Contents

Nios II Core Tab ..................................................................................................................................... 4–2

Core Setting ....................................................................................................................................... 4–2

Multiply & Divide Settings ............................................................................................................. 4–3

Caches & Tightly Coupled Memories Tab ......................................................................................... 4–4

Instruction Settings .......................................................................................................................... 4–4

Data Settings ..................................................................................................................................... 4–5

Advanced Features Tab ........................................................................................................................ 4–5

JTAG Debug Module Tab ..................................................................................................................... 4–6

Debug Level Settings ....................................................................................................................... 4–8

On-Chip Trace Buffer Settings ....................................................................................................... 4–9

Custom Instructions Tab .................................................................................................................... 4–10

Floating-Point Custom Instructions ............................................................................................ 4–10

Section II. Appendixes

Revision History ..................................................................................................................... Section II–1

Chapter 5. Nios II Core Implementation Details

Introduction ............................................................................................................................................ 5–1

Device Support ....................................................................................................................................... 5–2

Nios II/f Core ......................................................................................................................................... 5–3

Overview ........................................................................................................................................... 5–3

Register File ....................................................................................................................................... 5–3

Arithmetic Logic Unit ...................................................................................................................... 5–3

Memory Access ................................................................................................................................. 5–5

Tightly Coupled Memory ............................................................................................................... 5–7

Execution Pipeline ............................................................................................................................ 5–8

Instruction Performance .................................................................................................................. 5–9

Exception Handling ....................................................................................................................... 5–10

JTAG Debug Module ..................................................................................................................... 5–11

Unsupported Features ................................................................................................................... 5–11

Nios II/s Core ...................................................................................................................................... 5–11

Overview ......................................................................................................................................... 5–11

Register File ..................................................................................................................................... 5–12

Arithmetic Logic Unit .................................................................................................................... 5–12

Memory Access ............................................................................................................................... 5–13

Tightly Coupled Memory ............................................................................................................. 5–14

Execution Pipeline .......................................................................................................................... 5–15

Instruction Performance ................................................................................................................ 5–16

Exception Handling ....................................................................................................................... 5–17

JTAG Debug Module ..................................................................................................................... 5–17

Unsupported Features ................................................................................................................... 5–17

Nios II/e Core ...................................................................................................................................... 5–18

Overview ......................................................................................................................................... 5–18

Register File ..................................................................................................................................... 5–18

Arithmetic Logic Unit .................................................................................................................... 5–18