Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3B:
System Programming Guide, Part 2
NOTE: The Intel
®
64 and IA-32 Architectures Software Developer's Manual
consists of seven volumes: Basic Architecture, Order Number 253665;
Instruction Set Reference A-L, Order Number 253666; Instruction Set
Reference M-Z, Order Number 253667; Instruction Set Reference, Order
Number 326018; System Programming Guide, Part 1, Order Number
253668; System Programming Guide, Part 2, Order Number 253669;
System Programming Guide, Part 3, Order Number 326019. Refer to all
seven volumes when evaluating your design needs.
Order Number: 253669-040US
October 2011
ii Vol. 3B
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Vol. 3B 14-1
CHAPTER 14
POWER AND THERMAL MANAGEMENT
This chapter describes facilities of Intel 64 and IA-32 architecture used for power
management and thermal monitoring.
14.1 ENHANCED INTEL SPEEDSTEP
®
TECHNOLOGY
Enhanced Intel SpeedStep
®
Technology was introduced in the Pentium M processor;
it is available in Pentium 4, Intel Xeon, Intel
®
Core™ Solo, Intel
®
Core™ Duo, Intel
®
Atom™ and Intel
®
Core™2 Duo processors. The technology manages processor
power consumption using performance state transitions. These states are defined as
discrete operating points associated with different frequencies.
Enhanced Intel SpeedStep Technology differs from previous generations of Intel
SpeedStep Technology in two ways:
• Centralization of the control mechanism and software interface in the processor
by using model-specific registers.
• Reduced hardware overhead; this permits more frequent performance state
transitions.
Previous generations of the Intel SpeedStep Technology require processors to be a
deep sleep state, holding off bus master transfers for the duration of a performance
state transition. Performance state transitions under the Enhanced Intel SpeedStep
Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep
Technology is enabled by setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of
IA32_MISC_ENABLE MSR is cleared.
14.1.1 Software Interface For Initiating Performance State
Transitions
State transitions are initiated by writing a 16-bit value to the IA32_PERF_CTL
register, see Figure 14-2. If a transition is already in progress, transition to a new
value will subsequently take effect.
Reads of IA32_PERF_CTL determine the last targeted operating point. The current
operating point can be read from IA32_PERF_STATUS. IA32_PERF_STATUS is
updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications
and performance tools are not expected to use either IA32_PERF_CTL or
IA32_PERF_STATUS and should treat both as reserved. Performance monitoring
14-2 Vol. 3B
POWER AND THERMAL MANAGEMENT
tools can access model-specific events and report the occurrences of state
transitions.
14.2 P-STATE HARDWARE COORDINATION
The Advanced Configuration and Power Interface (ACPI) defines performance states
(P-state) that are used facilitate system software’s ability to manage processor
power consumption. Different P-state correspond to different performance levels
that are applied while the processor is actively executing instructions. Enhanced Intel
SpeedStep Technology supports P-state by providing software interfaces that control
the operating frequency and voltage of a processor.
With multiple processor cores residing in the same physical package, hardware
dependencies may exist for a subset of logical processors on a platform. These
dependencies may impose requirements that impact coordination of P-state transi-
tions. As a result, multi-core processors may require an OS to provide additional soft-
ware support for coordinating P-state transitions for those subsets of logical
processors.
A BIOS (following ACPI 3.0 specification) can choose to expose P-state as dependent
and hardware-coordinated to OS power management (OSPM) policy. To support
OSPMs, multi-core processors must have additional built-in support for P-state hard-
ware coordination and feedback.
Intel 64 and IA-32 processors with dependent P-state amongst a subset of logical
processors permit hardware coordination of P-state and provide a hardware-coordi-
nation feedback mechanism using IA32_MPERF MSR and IA32_APERF MSR. See
Figure 14-1 for an overview of the two 64-bit MSRs and the bullets below for a
detailed description:
• Use CPUID to check the P-State hardware coordination feedback capability bit.
CPUID.06H.ECX[Bit 0] = 1 indicates IA32_MPERF MSR and IA32_APERF MSR are
present.
• IA32_MPERF MSR (0xE7) increments in proportion to a fixed frequency, which is
configured when the processor is booted.
Figure 14-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination
63
0
IA32_MPERF (Addr: E7H)
630
IA32_APERF (Addr: E8H)
Vol. 3B 14-3
POWER AND THERMAL MANAGEMENT
• IA32_APERF MSR (0xE8) increments in proportion to actual performance, while
accounting for hardware coordination of P-state and TM1/TM2; or software
initiated throttling.
• The MSRs are per logical processor; they measure performance only when the
targeted processor is in the C0 state.
• Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software
should not attach meaning to the content of the individual of IA32_APERF or
IA32_MPERF MSRs.
• When either MSR overflows, both MSRs are reset to zero and continue to
increment.
• Both MSRs are full 64-bits counters. Each MSR can be written to independently.
However, software should follow the guidelines illustrated in Example 14-1.
If P-states are exposed by the BIOS as hardware coordinated, software is expected
to confirm processor support for P-state hardware coordination feedback and use the
feedback mechanism to make P-state decisions. The OSPM is expected to either save
away the current MSR values (for determination of the delta of the counter ratio at a
later time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at
the start of the time window used for making the P-state decision. When not reset-
ting the values, overflow of the MSRs can be detected by checking whether the new
values read are less than the previously saved values.
Example 14-1 demonstrates steps for using the hardware feedback mechanism
provided by IA32_APERF MSR and IA32_MPERF MSR to determine a target P-state.
Example 14-1. Determine Target P-state From Hardware Coordinated Feedback
DWORD PercentBusy; // Percentage of processor time not idle.
// Measure “PercentBusy“ during previous sampling window.
// Typically, “PercentBusy“ is measure over a time scale suitable for
// power management decisions
//
// RDMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between
// the two RDMSRs (for example, interrupts).
MCNT = RDMSR(IA32_MPERF);
ACNT = RDMSR(IA32_APERF);
// PercentPerformance indicates the percentage of the processor
// that is in use. The calculation is based on the PercentBusy,
// that is the percentage of processor time not idle and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.
// Note that both values need to be calculated over the same
// time window.
PercentPerformance = PercentBusy * (ACNT/MCNT);
