基于8086FPGA软核的吃豆子游戏

Run Pac-man Game Based on 8086/8088 FPGA IP Core

Authors: Kevin Xie, Michael Ye, Winston Zhu

Last update: 1

st

, August, 2007

Overview

On this page you will find a simple Pac-man game running on free FPGA IP Core of an 8086/8088

processor. This project consists of a CPU86 Core, three Memory Units and a VGA Controller Unit.

This system consumes 68% of logic slices, 2 GCLKs, 1Mult, 1 DCM and 100% of block RAMs which

is 40KB of Spartan-3E500 board, and can run at a frequency of up to 32.44MHz.

Attention: Downloading the following files means that you have read and accepted

the licenses listed above. Make sure your running a virus checker on the exe files

before executing them!

Download Hardware RTL Source Code files (version 1.0, 7.70MB, zipped);

Download Software C Code files (version 1.0, with comtool and bin2txt，444KB, zipped);

Function Description

When the CPU resets, it starts from address FFFF: 0000, just as a real 8086/8088 processor. After

cold start, the CPU fetches an instruction from the RAM in which Pac-man program resides,

executes that instruction, and writes data to the display buffer if needed, then fetches next

instruction iteratively. The VGA controller model reads data from display buffer, then generates

U_0: cpu86

The CPU86 Core consists of an 8088 Processor Core, an 8-bit Bus Interface Unit and a Hardware

Debug Unit. The hardware debug unit is used to interrogate the internal registers during single

stepping. The output of the debug unit is written in a DOS style format to a build-in fixed frame

UART. The CPU86 Core is fully binary/instruction compatible with an 8086/8088 processor, it is

however not cycle and timing accurate. For detailed information about CPU86, please refer to

U_1: superio

The superio model is a build-in fixed frame UART which defaults to 19200 Baud rate, no parity, 8