slan PFC芯片

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slan PFC芯片
APPLICATION NOTE C OVP Veao (L)-225V VmI ref MuLT3 Vm2IVref-Vref+2.5V Multiplier Vea(-) OVP Isovp-30uA Current Error Amp Detector Idovp=40uA vm1·(vm2-Vref) EA OUT Figure 4. Multiplier block 2-3. Current Sense Comparator start-up at extremely high line or as output voltage sensing is The current sense comparator adopts the rs latch lost. Under these conditions, the multiplier output and configuration to ensure that only a single pulse appears at the current sense threshold will be internally clamped to 1. 8V drive output during a given cycle. mosfet drain current is Therefore, the maximum peak switch current is limited to sensed using an external sense resistor in series with the Ipk(max)=1.8V/Rsense external MOSFET. When the sensed voltage exceeds the In the sa7527. an internal R/C filter has been included to comparator turns off the mosfet and resets the pwm attenuate any high frequency noise that may be present on latch. The latch ensures that the output remains in a low state the current waveform This circuit block eliminates the need after the mosfet drain current falls back to zero for an external r/c filter otherwise required for proper The peak inductor current under the normal operating operation of the circuit condition is controlled by thc multiplier output, Vmo. The abnormal operating condition occurs during pre-converter CS 40k 8pF sRsense Current sense Comparator 1. 8V Figure 5. Current Sense Circuit 3 APPLICATION NOTE 2-4 Zero current detector provided The zero current detector input is protected SA7527 operates as a critical conduction current mode internally by two clamps. The upper 7.2V clamp prevents controller. The zero current detector switches on the external mput over voltage breakdown while the lower 0. 75v clamp MOSFET as the voltage across the boost inductor reverses prevents substrate injection. An internal current limit resistor ust after the current through the boost inductor has gone to protects the lower clamp transistor in case the Idet pin is zero. The slope of the inductor current is indirectly detected horted to ground accidentally. a watchdog timer function is y monitoring the voltage across an auxiliary winding and added to the ic to eliminate the need for an external connecting it to the zero current detector Pin 5 oscillator when used in stand-alone applications. The timer Oncc thc inductor current reaches ground lcvcl, thc polarity provides a means to start or restart the pre-converler of the voltage across the winding is reversed. when the ldet automatically if the drive output has been off for more than input falls below 1.5V, the comparator output is triggered to I 50us after the inductor current reached zero the low state. To prevent false tripping, 0.5V hysteresis is Vin Idet TO F/H 72v 21.5V Zero current Detector Figure 6. Zero Current Detector Block 2-5 Output Drive switching frequency limitation. The minimum switching The sa7527 contains a single totem-pole output stage trequency has to be above the audio frequency designed specifically for a direct drive of power mOsfet The switching period is maximum when the input voltage is The drive output is capable of up to 500ma peak current highest at maximum load condition. TS(max) is a function o with a 1.OnF load. Additional circuitry has been added to a (peak) and vo. It can have maximum value at highest line with a typical risc and fall timc of 130ns, 5Ons respcctivcl at lowest line according to Vo. Check Ts max at keep the drive output in a sinking mode whenever the UVLO in(peak_min) andⅤ peak_max), then take the higher value is active. This characteristic eliminates the need for an for the maximum switching period. The boost inductor value external gate pull-down resistor: Internal voltage clamping can bc obtaincd by(5) ensures that the output driver is always lower than 14V when supply voltage exceeds the rated vgs of the external MOSFET. This eliminates an external zener diode and extra power dissipation associated with it that otherwise is -L(peak)=l-in(peak sin(at) required for the reliable circuit operation in(peak) sin(ot) in(peak)in(ot (1) 3. Circuit Components Design in (peak) 3-1. Power stage design 1)Boost inductor design The boost inductor value is determined by the minimum APPLICATION NOTE 2) Auxiliary winding design (2) o-Vin(peas)sin(ot) The auxiliary winding voltage is lowest at the highest line So the number of auxiliary winding can be obtained by (7) 2I in(peak) Sin(ot) V⌒·N1 C vOlo aux in(pcak) (3) v-221 n(HL) 3)Input capacitor design s onoff sin(oot) 2Llin(peakS. (4) The voltage ripple of the input capacitor is maximum when n(peak)o in(peak, sin(ot)/ the line is lowest and the load is heaviest. If fsw(min)>> fac 4LV OO(max the input current can be assumed to be constant during a witching pe 4LV s(max) in(peak)ˇin(peak)o-ˇin(peek (6) sw(min oo(max) n(peak)in(peak)(Vo -in(peak)) Inductor Current Current n(peak max) Figure 7. Input Current and Inductor Current Waveform during a Switching cycle 2 (ot)(9) I[L(lld ia la cos(ot) in(peak max) t dt ic=la cos(ot)-oCin Vin(peak) sin(ot) (10) n 9= ta on in(peak max in IoC (11) L·Io(max)V in(max) tan( cos (IDF)) in(peak) in(peak_max) volo (IDF)(12 The input capacitor must be larger than the value calculated by(8). And the maximum input capacitance is limited by the input displacement factor(IDF), defined as IDF=coSO There fore the input capacitor must be smaller than Cin(max) calculated by(12) 5 APPLICATION NOTE r: LA 十 十 PFC Circuit e Re Input Filter Figure 8 Input voltage and current displacement due to input filter capacitance 4)Output capacitor design The output capacitor is determined by the relation between the input power and the output power. As shown in Fig. 10, O(max) Co(mi)2fac·o(max) (14) the minimum output capacitance is determined by(14) 5) MOSFET and diode selection Maximum MOSFET Ims current is obtained by (15 )and the PFC conduction loss of the mosfet is calculated by(16).When 十 MOSFET turns on the MOsFET current rises slowly so the C e o turn on loss is negligible. MOSFET turn off loss and MOSFET discharge loss are obtained by (17)and (18) respectively. The switching frequency of the critical conduction mode boost PFC converter varies according to Figure 9. PFC configuration the line condition and load condition Therefore the switching frcqucncy is thc avcragc valuc during a linc (rms) Vir(ns(1-cos(2ot))=IDVo period. The total MOSFET loss can be calculated by(19 Iin(ras) in(rm5(1-cos(2ot)) and then a MOSFET can be selected considering mOsFet thermal characteristic lo(-cos(2ot)) L(peak_mEx) 69 In(ve)=lo(1-cos(2ot)) 2/ 2.Volo(max)1 4; m vi (15) 6 9≠V (16) urn-o L(peak_max)fsw oCo discharge 3 18) MOSFET P+P turn-off +P discharge 19 And the MOSFET gate drive resistor is determined by(20) Figure 10. Diode current and output voltage waveform APPLICATION NOTE Omax 16V 32 500mA (20) in(peak_min)th(st)max The valuc is calculated on the assumption that the Rst v in(rms-max)"1W (27) gate-source voltage should be a square waveform, 1. e, abrupt changes with no rising or falling time Thus the drive current can not reach 500ma during the rising (ST)IIi or falling time although rg of 32 is used The recommended rst values according to cst values are 10 is recommended as thc Rg in order to the MOSFet shown on tablc l. To make the vcc voltage stable, usc ro switching loss. The experimental results shows that the gate values listed on the table or lower RsT values than the listed peak current goes up to 300mA with 10 values. Higher Rst values can cause the system unstable Diode average current can be calculated by (21). The total therefore don' t use higher rst values diode loss can be calculated by(22)and then a diode can be elected considering diode thermal characteristic Table 1: recommended r ed rst, cst values C ST st o(max (21) Diode v Davg (22) 22uF 100k 33uF 120k 3-2. Control circuit design 1)Output voltage sensing resistor and feedback loop desi 47uF 120k sIs determined by the maximum output over voltage R 68uF 120k oyp and r2 is determined by(23) 2.5 4)Line voltage sense resistor and current sense resistor R NOVP design 2.5 40∞A The maximum line voltage sensing gain is determined by 2.5R (23) (29)at the highest line 2Vo-2.5 The feedback loop bandwidth must be narrower than 20Hz for the pfc application. Therefore a capacitor is connected PIN3 in(peak_max)R.+R between INV and EA OUt to eliminate the 120Hz ripple voltage by 40dB. The error amp compensation capacitor can Vin(peak_max). Gin(max)$3.8V be calculated by(24). To improve the power factor, CCOme Calculate the pin 3 voltage at the lowest line using Gin(max) must be increased than the calculated value. and to improve by(30). Then the current sense resistor is determined by the system response, Ccomp must be lowered than the 1),(32)and (34). Once the current sense resistor is calculated value determined, then the minimum line voltage sensing gain, ermined by (31) Ccomp=0.01.2≠.120H2.R,(24) O(m)=k v 2) Zero current detection resistor design in(peak_min)R. +R.Vm2 (max)(30) in2 Idet current should be less than 3mA. therefore zero current sense K. V detection resistor is determined by (25) in(peak_min)R L(peak_max) mV .2.5V in(peak_min) (31) aux Np:·3mA OO(max) 1. 8V n 3)Start-up circuit design Senses To start-up the SA7527B, the start-up current must be L(peak_max) 1.8V 4.0o(max) supplied through a start- up resistor. The resistor valuc is 2 0O(max) 2 calculated by(26)and(27). The start-up capacitor must Rsense mv in(peak_miny sense <1w supply ic operating current before the auxiliary winding supplies ic operating current maintaining Vcc voltage higher 1(n sense 2 than the UVLO voltage. Therefore the start-up O(max) capacitor is designed by(28) APPLICATION NOTE And attach InF capacitor in parallel with r2 to reduce the 4-7. Start-up circuit design switching ripple voltage The maximum start-up resistor is 1 M and the minimum is 70k by(26)-(27). Our selection is 120k. And the 4. Design EXample start-up capacitance must be larger than 10.6uF by(28). The A 100w converter is designed to illustrate the design proce selected value is 47uF dure. The system parameters are as follows 4-8 Line voltage sense resistor and current Maximum output power: 100W sense resistor design Input voltage range 85 Vrms-265 Vrms The maximum input voltage sensing gain is determined by Output voltage 400V (29). Using the calculated value, the current sense resistance AC line frequency: 60Hz is determined by (31),(32)and (34). The maximum current ° PFC efliciency 90% sense resistance is 0.48 and the selected value is 0.4 Minimum switching frequency: 33kHZ Then the minimum input voltage sensing gain is determined Input displacement factor(IDF): 0.97 by(30). If we choose the input voltage sense bottom resistor Input capacitor ripple voltage: 24V to be 22k then the maximum input voltage sense upper Output voltage ripple: 8 resistance and the minimum input voltage sense upper OVP set vollage: 440V resistance can be obtained from g n(min)and g The selected value is 1.8M 4-1. Inductor design Fig. 1l shows the designed application circuit diagram and The boost inductor is determined by(6) Calculate it at both table 2-11 show the application circuit components lists of the lowest line and the highest line and choose the lower 32W. 64W. 100w. 150w and 200W application value. The calculated value is 604uH. To get the calculate inductor value, El3026 core is used and the primary winding is 58 turns. The air gap is 0. 80mm at both legs of the EI core The auxiliary winding is determined by (7)and the auxiliary winding is 4 turns 4-2. Input capacitor design The minimum input capacitance is determined by the input voltage ripple spccification. The calculatcd minimum input capacitor value is 0.5SuF And the maximum input capacitance is restricted by IDF. The calculated value is le selected value is 0. 88uF for the in capacitors(sum of all capacitors connected to the input) 4-3. Output capacitor design The minimum output capacitor is determined by (14) and the calculatcd valuc is 83uF. Thc sclccted valuc is 100uF capacitor 4-4. MOSFET and diode selection By(15)-(19), 500V/4.6A MOSFET IRFS840B is selected and by (21)(23), and 600V/la diode byv26C is selected by(21)(22 4-5 Output voltage sense resistor and feedback loop design The upper output voltage sense resistor is 1.0M|and the bottom output voltage sense resistor is 6k plus 10k variable resistor. A variable resistor is used to adjust the output voltage. To improve the power factor, the error amp compensation capacitance must be larger than 0. 132uF by (24). Therefore luF capacitor is used 4-6. Zero current detection resistor design The calculate value is 430 and the selected value is 22k APPLICATION NOTE TI D2 C5 R32 R5 BDI ≤R8 R6 DI Q1 NTC R13 D3 C3 C4 c8 C6 C2 LFI SA7527 Ro R7 多R1 F1 C7 R2 AC INPUT Figure 11. Application circuit diagram APPLICATION NOTE Table 2: SA7527 32W Wide-Range Application Circuit Components list Part Number Value Note Manufacturer R1 1.8N 1/4W R2 22k 1/4W R3 120k 1W R5 22k 1/4W R6 10 14W R7 133 1W R8 1M 1/4W R9 6k 1/4W VR1 103 Variable resistor C1 47nF. 275vac Box-Cap C2 100nF. 275vac BoX-Cal C3.4 2200pF,3000V Y-Cap C5 0.1a,630V Miller-Cap C6 47∝F,35V Electrolytic C7 1∝F MLCC C8 22F,450V Electrolytic c9 1nF 25V Ceramic BD1 600V4A Bridge Diode D1,3 75V,150mA 1N4148 D2 600V.1A BYV26C LF 1 45mH Line filter 1.84mH(140T:11T E|2519 Q1 500V,23A FQPF4N50 250V.3A Fuse V1 470V 471 NTC 10D09 10

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