================================
Welcome to Electronics Workbench
================================
The Release Notes contain important information that was
received too late to be included in the written documentation.
They can be found in the online help. To view the release
notes, start Electronics Workbench and choose Release Notes
from the Help menu.
Below is further information which was too late to be included
in the online Help.
================================================================
Parser Errors Tab
A new tab has been added to the Analysis Graphs Window, called
"Parser Errors". The tab appears only if errors occur during
the parsing of a subcircuit netlist model. (Note: Parsing
occurs after you start a simulation or analysis.)
Most of the errors appearing in this list are only warnings.
They simply notify the user of syntax in a netlist which is
unsupported by Electronics Workbench.
================================================================
Electronics Workbench User's Guide Corrections
Page 5-2 - The circuit under Step 1 shows the first connection
of the word generator connected to connector "S" and the second
connection of the word generator connected to connector "R".
This is reversed. The first connection of the word generator
should be connected to connector "R" and the second to
connector "S".
Page 5-4 - The second point under Step 3 should state "Change
the frequency to 1 MHz".
Page 5-5 - The circuit under Step 1 shows the first connection
of the word generator connected to connector "S" and the second
connection of the word generator connected to connector "R".
This is reversed. The first connection of the word generator
should be connected to connector "R" and the second to
connector "S".
The procedure for setting the logic analyzer under Step 1 is no
longer correct as the logic analyzer was revised after the
printing of the User's Guide and Technical Reference.
The new procedure for setting the Logic Analyzer is as follows:
1. Set the frequency of the word generator to 1 MHz.
2. On the logic analyzer, set the clocks per division to 1.
3. Click on the set button in the clock box and ensure the
following:
- Clock edge "negative"
- Clock mode "internal"
- Set internal clock rate to "1 MHz"
- Clock qualifier "x"
- Logic analyzer "Pre-trigger samples 100"
"Post-trigger samples 1000"
"Threshold voltage (V) 3.5"
4. Make sure the Current address on the word generator is 0000.
5. Click the Cycle button on the word generator.
================================================================
Technical Reference Corrections
PAGE 14-22 - The picture of the opened logic analyzer is
incorrect. Since the manual was printed, the Time Base feature
has been removed and replaced with a Clocks per division
feature.
The "Time base" setting was used to set the logic analyzer's
display in units of seconds/division. The "Clocks per division"
setting is used to set the traces in units of clocks/division.
The number of clocks refers to the number of samples of the
data from the input terminals which have been taken.
Page 14-23 - The third paragraph discusses how to specify the
number of samples stored before and after triggering. The user
can also specify the number of samples by selecting the set
button in the clock box of the logic analyzer and making the
appropriate changes.
================================================================
Electronics Workbench is a registered trademark of Interactive
Image Technologies Ltd.
Copyright (c) Interactive Image Technologies Ltd., 1996.
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EWB50软件小型的仿真软件
共764个文件
ewb:350个
lib:207个
m15:53个
需积分: 9 5 下载量 187 浏览量
2009-11-07
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EWB50软件小型的仿真软件 (764个子文件)
INFO.BAT 937B
GLOBAL.CNF 569B
GLOBAL.CNF 486B
EWBEXT.CNF 251B
EWB.CSP 288B
XSPICE32.DLL 1.22MB
GRAPHER.DLL 528KB
SPICEEWB.DLL 137KB
COMPDAT.DLL 131KB
ANALOG.DLL 126KB
EWBSPICE.DLL 102KB
CHIP.DLL 82KB
EWBTOPCB.DLL 81KB
DIGITAL.DLL 68KB
GETRES32.DLL 23KB
GETRES16.DLL 8KB
实用开方运算电路.ewb 1.04MB
mc1595模拟相乘器混频器.ewb 480KB
文件2.ewb 433KB
mc1595模拟相乘器调幅.ewb 432KB
mc1595模拟相乘器的馈通误差电压调零.ewb 416KB
实用除法器电路.ewb 389KB
mc1595模拟相乘器的乘法和平方运算电路.ewb 357KB
mc1595(bg314)四象限模拟相乘器.ewb 329KB
mc1595四象限模拟相乘器的调试.ewb 329KB
基于ota(ca3080)的模拟乘法器.ewb 170KB
乘法器检相器仿真.ewb 157KB
基于ota(ca3080)的采样保持电路.ewb 130KB
基于ota(ca3080)的电压放大电路.ewb 118KB
单级放大器原理电路.ewb 106KB
ne555内部电路.ewb 94KB
高频电路考题.ewb 89KB
mc1596模拟相乘器鉴相仿真.ewb 87KB
倍频.ewb 78KB
绝对值电路.ewb 77KB
调幅.ewb 76KB
间接调相,调频电路仿真.ewb 75KB
fm鉴频.ewb 74KB
双边带同步检波.ewb 73KB
直接调频,调相仿真.ewb 64KB
二级共发-共基中频放大电路.ewb 62KB
调幅1.ewb 62KB
mc1594l四象限模拟相乘器.ewb 59KB
单片ota(ca3080)电路.ewb 58KB
环型二极管混频电路.ewb 54KB
二极管平衡同步检波电路仿真.ewb 53KB
变容二极管调相电路.ewb 51KB
调频器.ewb 51KB
典型实用电路.ewb 50KB
耦合回路.ewb 50KB
变容二极管间接调频原理电路.ewb 45KB
窄带石英晶体滤波器电路仿真.ewb 43KB
文氏电桥振荡器.ewb 42KB
lc耦合振荡电路仿真.ewb 41KB
互感耦合回路.ewb 39KB
具有温度补偿的对数放大器.ewb 38KB
阻抗变换.ewb 38KB
pll.ewb 37KB
高频功放原理电路.ewb 37KB
习题四.ewb 37KB
RAM.EWB 36KB
放大器y参数等效电路.ewb 36KB
并联限幅电路.ewb 36KB
二极管双向限幅电路.ewb 36KB
串联限幅电路.ewb 36KB
变容二极管直接调频原理电路.ewb 34KB
l型网络的阻抗变换.ewb 34KB
常用抽头振荡电路.ewb 33KB
正交型鉴相器的仿真.ewb 33KB
等效变换电路.ewb 33KB
seiler oscillator仿真.ewb 32KB
时变线形跨导电路.ewb 32KB
mc1596模拟相乘器混频的仿真.ewb 32KB
mc1595l(bg314)四象限模拟相乘器.ewb 32KB
集电极串馈和并馈电路.ewb 32KB
ne555单稳态电路.ewb 31KB
UA709.EWB 31KB
50毫秒单脉冲.ewb 31KB
射频前置放大.EWB 30KB
untitled.ewb 30KB
二极管桥式死区电路.ewb 30KB
射频前置放大电路.EWB 30KB
两极差动放大器频率特性分析.ewb 30KB
二极管电桥调幅电路仿真.ewb 30KB
自给偏压基极偏置电路.ewb 29KB
二极管同步检波器仿真.ewb 29KB
mc1596双边带同步检波.ewb 29KB
有源带阻滤波器.ewb 28KB
占空系数可调的方波信号生器.ewb 28KB
晶体管倍频器.ewb 28KB
带通滤把波器.ewb 28KB
带电流源负载的差分电路.ewb 27KB
高频功率放大器原理电路.ewb 26KB
文氏电桥正弦波发生器实用电路.ewb 26KB
三位二进制编码器.EWB 26KB
dvccii的电路实现.ewb 26KB
二极管混频平衡电路仿真.ewb 26KB
mc1596模拟相乘器.ewb 26KB
二级电压串联负反馈放大器电路图.ewb 26KB
奇偶校验电路.EWB 26KB
共 764 条
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