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04_Demo Reference Design.rar （6个子文件）

04_Demo Reference Design

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228.DSN 4.59MB

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228-162.DSN 16.75MB

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228_Modify_Notes_CN.pdf 1.61MB

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228_final_lint.brd 20.98MB

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228.pdf 1.92MB

RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228_final_lint阻抗叠层.xls 589KB

<html xmlns="http://www.w3.org/1999/xhtml"><head><meta charset="utf-8"><meta name="generator" content="pdf2htmlEX"><meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/base.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/85084630/raw.css"><script src="https://csdnimg.cn/release/download_crawler_static/js/compatibility.min.js"></script><script src="https://csdnimg.cn/release/download_crawler_static/js/pdf2htmlEX.min.js"></script><script>try{pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({});}catch(e){}</script><title></title></head><body><div id="sidebar" style="display: none"><div id="outline"></div></div><div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/85084630/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m0 x2 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">4</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">4</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m0 x3 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m0 x4 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m0 x4 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m0 x5 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1</div><div class="t m0 x5 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">1</div><div class="t m0 x6 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0">D<span class="_ _0"> </span>D</div><div class="t m0 x6 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0">C<span class="_ _0"> </span>C</div><div class="t m0 x6 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">B<span class="_ _1"> </span>B</div><div class="t m0 x6 h2 y6 ff1 fs0 fc0 sc0 ls0 ws0">A<span class="_ _1"> </span>A</div><div class="t m0 x7 h3 y7 ff2 fs1 fc0 sc0 ls0 ws0">19) Sup<span class="_ _2"></span>port: Debug UA<span class="_ _2"></span>RT(USB to UART)<span class="_ _2"></span>,Debug J<span class="_ _2"></span>TAG (4Pin)</div><div class="t m0 x7 h3 y8 ff2 fs1 fc0 sc0 ls0 ws0">17) Sup<span class="_ _2"></span>port: 1 x RS<span class="_ _2"></span>485</div><div class="t m0 x7 h3 y9 ff2 fs1 fc0 sc0 ls0 ws0">18) Sup<span class="_ _2"></span>port: 1 x UART</div><div class="t m0 x7 h3 ya ff2 fs1 fc0 sc0 ls0 ws0">10) Sup<span class="_ _2"></span>port: 2 x 10/10<span class="_ _2"></span>0/1000 Ethern<span class="_ _2"></span>et(RGMII)</div><div class="t m0 x7 h3 yb ff2 fs1 fc0 sc0 ls0 ws0">13) Sup<span class="_ _2"></span>port: 1 x I<span class="_ _2"></span>R Receiv<span class="_ _2"></span>er</div><div class="t m0 x7 h3 yc ff2 fs1 fc0 sc0 ls0 ws0">11) Sup<span class="_ _2"></span>port: 1 x Lin<span class="_ _2"></span>e Out, 1 <span class="_ _2"></span>x Line In</div><div class="t m0 x7 h3 yd ff2 fs1 fc0 sc0 ls0 ws0">14) Sup<span class="_ _2"></span>port: 1 x Power<span class="_ _2"></span> LED,1 x E<span class="_ _2"></span>thernet LED,1 x HDD<span class="_ _2"></span> LED</div><div class="t m0 x7 h3 ye ff2 fs1 fc0 sc0 ls0 ws0">12) Sup<span class="_ _2"></span>port: 1 x Bu<span class="_ _2"></span>zzer</div><div class="t m0 x7 h3 yf ff2 fs1 fc0 sc0 ls0 ws0">15) Sup<span class="_ _2"></span>port: 1 x Recov<span class="_ _2"></span>ery Key,1x <span class="_ _2"></span>Reset Key</div><div class="t m0 x7 h3 y10 ff2 fs1 fc0 sc0 ls0 ws0">16) Sup<span class="_ _2"></span>port: 1 x RS<span class="_ _2"></span>232</div><div class="t m0 x8 h3 y11 ff2 fs1 fc0 sc0 ls0 ws0">9) Sup<span class="_ _2"></span>port: 2 x 4La<span class="_ _2"></span>nes MIPI <span class="_ _2"></span>CSI RX <span class="_ _2"></span>Camera Connector</div><div class="t m0 x9 h4 y12 ff3 fs2 fc1 sc0 ls0 ws0">RK_NVR_DEMO1_RK35<span class="_ _2"></span>88_LP<span class="_ _2"></span>4XD200P<span class="_ _2"></span>232S<span class="_ _2"></span>D8_V21</div><div class="t m0 x9 h5 y13 ff3 fs3 fc2 sc0 ls0 ws0">Main Functions Introduction</div><div class="t m0 x8 h3 y14 ff2 fs1 fc0 sc0 ls0 ws0">5) Sup<span class="_ _2"></span>port: 1 x USB3.<span class="_ _2"></span>0 HOST + <span class="_ _2"></span>2 x USB2.0 <span class="_ _2"></span>HOST</div><div class="t m0 x8 h3 y15 ff2 fs1 fc0 sc0 ls0 ws0">7) Sup<span class="_ _2"></span>port: 1 x 4La<span class="_ _2"></span>nes PCIe Connector</div><div class="t m0 x8 h3 y16 ff2 fs1 fc0 sc0 ls0 ws0">8) Sup<span class="_ _2"></span>port: 2 x HDMI<span class="_ _2"></span>2.1 TX + <span class="_ _2"></span>1 x HDMI2.<span class="_ _2"></span>0 TX + 1 x HD<span class="_ _2"></span>MI1.4 TX</div><div class="t m0 xa h6 y17 ff3 fs4 fc0 sc0 ls0 ws0">Schematics Onl<span class="_ _2"></span>y f<span class="_ _2"></span>or RK3588 NV<span class="_ _2"></span>R</div><div class="t m0 x8 h3 y18 ff2 fs1 fc0 sc0 ls0 ws0">2) RAM: <span class="_ _2"></span> 2 <span class="_ _2"></span>x LPDDR4x 32bi<span class="_ _2"></span>t(Opti<span class="_ _2"></span>on 2 x LPDDR4 <span class="_ _2"></span>32bit)</div><div class="t m0 x8 h3 y19 ff2 fs1 fc0 sc0 ls0 ws0">3) ROM:<span class="_ _2"></span> eM<span class="_ _2"></span>MC5.1(Opti<span class="_ _2"></span>on SPI Nan<span class="_ _2"></span>d Fal<span class="_ _2"></span>sh)</div><div class="t m0 x8 h3 y1a ff2 fs1 fc0 sc0 ls0 ws0">6) Sup<span class="_ _2"></span>port: 10 x S<span class="_ _2"></span>ATA3.0 Connector <span class="_ _2"></span>(7pin)</div><div class="t m0 x8 h3 y1b ff2 fs1 fc0 sc0 ls0 ws0">1) PMIC:<span class="_ _2"></span> RK<span class="_ _2"></span>806-1+Dis<span class="_ _2"></span>cretePower</div><div class="t m0 x8 h3 y1c ff2 fs1 fc0 sc0 ls0 ws0">4) Sup<span class="_ _2"></span>port: 1 x TypeC(<span class="_ _2"></span>With DP <span class="_ _2"></span>TX)</div><div class="t m0 x7 h7 y1d ff4 fs5 fc0 sc0 ls0 ws0">The RK806 LDO power distribution of the reference schematics </div><div class="t m0 x7 h7 y1e ff4 fs5 fc0 sc0 ls0 ws0">is only suitable for the interface used in </div><div class="t m0 x7 h7 y1f ff4 fs5 fc0 sc0 ls0 ws0">the reference schematics. </div><div class="t m0 x7 h7 y20 ff4 fs5 fc0 sc0 ls0 ws0">If other interface functions are to be added to </div><div class="t m0 x7 h7 y21 ff4 fs5 fc0 sc0 ls0 ws0">the reference schematics, the RK806 LDO distribution </div><div class="t m0 x7 h7 y22 ff4 fs5 fc0 sc0 ls0 ws0">needs to be re evaluated, otherwise the added </div><div class="t m0 x7 h7 y23 ff4 fs5 fc0 sc0 ls0 ws0">functions may exceed the maximum current </div><div class="t m0 x7 h7 y24 ff4 fs5 fc0 sc0 ls0 ws0">provided by the LDO</div><div class="t m0 x7 h8 y25 ff4 fs6 fc3 sc0 ls0 ws0">Note:</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Wednesday, December 22, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">00.Cover Page</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">1<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Wednesday, December 22, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">00.Cover Page</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">1<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Wednesday, December 22, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">00.Cover Page</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">1<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div></div><div class="pi" data-data='{"ctm":[1.140251,0.000000,0.000000,1.140251,0.000000,0.000000]}'></div></div></body></html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/85084630/bg2.jpg"><div class="t m0 x13 he y2f ff1 fsc fc0 sc0 ls0 ws0">5</div><div class="t m0 x13 he y30 ff1 fsc fc0 sc0 ls0 ws0">5</div><div class="t m0 x14 he y2f ff1 fsc fc0 sc0 ls0 ws0">4</div><div class="t m0 x14 he y30 ff1 fsc fc0 sc0 ls0 ws0">4</div><div class="t m0 x15 he y2f ff1 fsc fc0 sc0 ls0 ws0">3</div><div class="t m0 x15 he y30 ff1 fsc fc0 sc0 ls0 ws0">3</div><div class="t m0 x16 he y2f ff1 fsc fc0 sc0 ls0 ws0">2</div><div class="t m0 x16 he y30 ff1 fsc fc0 sc0 ls0 ws0">2</div><div class="t m0 x17 he y2f ff1 fsc fc0 sc0 ls0 ws0">1</div><div class="t m0 x17 he y30 ff1 fsc fc0 sc0 ls0 ws0">1</div><div class="t m0 x6 he y31 ff1 fsc fc0 sc0 ls0 ws0">D<span class="_ _5"> </span>D</div><div class="t m0 x6 he y32 ff1 fsc fc0 sc0 ls0 ws0">C<span class="_ _5"> </span>C</div><div class="t m0 x6 he y33 ff1 fsc fc0 sc0 ls0 ws0">B<span class="_ _5"> </span>B</div><div class="t m0 x6 he y34 ff1 fsc fc0 sc0 ls0 ws0">A<span class="_ _5"> </span>A</div><div class="t m0 x18 hf y35 ff3 fsd fc3 sc0 ls0 ws0">Notes</div><div class="t m0 x19 h10 y36 ff3 fse fc1 sc0 ls0 ws0">Table of Content</div><div class="t m0 x1a h11 y37 ff6 fsf fc3 sc0 ls0 ws0">NOTE 1<span class="ff7 sc1">：</span></div><div class="t m0 x1a h12 y38 ff6 fsf fc3 sc0 ls0 ws0">Component parame<span class="_ _2"></span>ter des<span class="_ _2"></span>cription</div><div class="t m0 x1a h12 y39 ff6 fsf fc3 sc0 ls0 ws0">1. DNP sta<span class="_ _2"></span>nds for component <span class="_ _2"></span>not moun<span class="_ _2"></span>ted te<span class="_ _2"></span>mporarily</div><div class="t m0 x1a h12 y3a ff6 fsf fc3 sc0 ls0 ws0">2. If Value or opt<span class="_ _2"></span>ion is D<span class="_ _2"></span>NP, which mea<span class="_ _2"></span>ns the <span class="_ _2"></span>area is rese<span class="_ _2"></span>rved with<span class="_ _2"></span>out </div><div class="t m0 x1a h12 y3b ff6 fsf fc3 sc0 ls0 ws0"> being <span class="_ _2"></span>mounted</div><div class="t m0 x1a h12 y3c ff6 fsf fc3 sc0 ls0 ws0">NOTE 2:</div><div class="t m0 x1a h12 y3d ff6 fsf fc3 sc0 ls0 ws0">Please us<span class="_ _2"></span>e our recommende<span class="_ _2"></span>d components<span class="_ _2"></span> to av<span class="_ _2"></span>oid too man<span class="_ _2"></span>y changes.</div><div class="t m0 x1a h12 y3e ff6 fsf fc3 sc0 ls0 ws0">For more informations<span class="_ _2"></span> about th<span class="_ _2"></span>e se<span class="_ _2"></span>cond source,please<span class="_ _2"></span> refer to our AVL.</div><div class="t m0 x1a h13 y3f ff3 fs10 fc0 sc0 ls0 ws0">Combined property string:</div><div class="t m0 x1a h13 y40 ff3 fs10 fc0 sc0 ls0 ws0">Header:</div><div class="t m0 x1a h12 y41 ff2 fsf fc0 sc0 ls0 ws0">{Item}\t{Value}\t{Descr<span class="_ _2"></span>iption}\t{PCB Footprint}\t{Refer<span class="_ _2"></span>ence}\t{Quantity}\t{Option}</div><div class="t m0 x1a h12 y42 ff2 fsf fc0 sc0 ls0 ws0">Item\tPart\tDescription\t<span class="_ _6"></span>PCB Footpr<span class="_ _2"></span>int\tReference\tQuantit<span class="_ _6"></span>y\tOption</div><div class="t m0 x1a hf y43 ff3 fsd fc0 sc0 ls0 ws0">Generate Bill of M<span class="_ _2"></span>aterial<span class="_ _2"></span>s</div><div class="t m0 x1b h12 y44 ff8 fsf fc0 sc0 ls0 ws0">Page 2</div><div class="t m0 x1b h12 y45 ff8 fsf fc0 sc0 ls0 ws0">Page 3</div><div class="t m0 x1b h12 y46 ff8 fsf fc0 sc0 ls0 ws0">Page 4</div><div class="t m0 x1b h12 y47 ff8 fsf fc0 sc0 ls0 ws0">Page 5</div><div class="t m0 x1b h12 y48 ff8 fsf fc0 sc0 ls0 ws0">Page 6</div><div class="t m0 x1b h12 y49 ff8 fsf fc0 sc0 ls0 ws0">Page 7</div><div class="t m0 x1b h12 y4a ff8 fsf fc0 sc0 ls0 ws0">Page 8</div><div class="t m0 x1b h12 y4b ff8 fsf fc0 sc0 ls0 ws0">Page 9</div><div class="t m0 x1b h12 y4c ff8 fsf fc0 sc0 ls0 ws0">Page 10</div><div class="t m0 x1c h12 y4d ff8 fsf fc0 sc0 ls0 ws0">00.Cover<span class="_ _2"></span> Page</div><div class="t m0 x1c h12 y44 ff8 fsf fc0 sc0 ls0 ws0">01.Index and Notes</div><div class="t m0 x1b h12 y4e ff8 fsf fc0 sc0 ls0 ws0">Page 11</div><div class="t m0 x1b h12 y4f ff8 fsf fc0 sc0 ls0 ws0">Page 12</div><div class="t m0 x1b h12 y50 ff8 fsf fc0 sc0 ls0 ws0">Page 13</div><div class="t m0 x1b h12 y51 ff8 fsf fc0 sc0 ls0 ws0">Page 14</div><div class="t m0 x1b h12 y52 ff8 fsf fc0 sc0 ls0 ws0">Page 15</div><div class="t m0 x1b h12 y53 ff8 fsf fc0 sc0 ls0 ws0">Page 16</div><div class="t m0 x1b h12 y54 ff8 fsf fc0 sc0 ls0 ws0">Page 17</div><div class="t m0 x1b h12 y55 ff8 fsf fc0 sc0 ls0 ws0">Page 18</div><div class="t m0 x1b h12 y56 ff8 fsf fc0 sc0 ls0 ws0">Page 19</div><div class="t m0 x1b h12 y57 ff8 fsf fc0 sc0 ls0 ws0">Page 20</div><div class="t m0 x1b h12 y1a ff8 fsf fc0 sc0 ls0 ws0">Page 21</div><div class="t m0 x1b h12 y58 ff8 fsf fc0 sc0 ls0 ws0">Page 22</div><div class="t m0 x1b h12 y59 ff8 fsf fc0 sc0 ls0 ws0">Page 23</div><div class="t m0 x1b h12 y5a ff8 fsf fc0 sc0 ls0 ws0">Page 24</div><div class="t m0 x1b h12 y5b ff8 fsf fc0 sc0 ls0 ws0">Page 25</div><div class="t m0 x1b h12 y5c ff8 fsf fc0 sc0 ls0 ws0">Page 26</div><div class="t m0 x1b h12 y5d ff8 fsf fc0 sc0 ls0 ws0">Page 27</div><div class="t m0 x1b h12 y5e ff8 fsf fc0 sc0 ls0 ws0">Page 28</div><div class="t m0 x1b h12 y5f ff8 fsf fc0 sc0 ls0 ws0">Page 29</div><div class="t m0 x1b h12 y60 ff8 fsf fc0 sc0 ls0 ws0">Page 30</div><div class="t m0 x1b h12 yb ff8 fsf fc0 sc0 ls0 ws0">Page 31</div><div class="t m0 x1b h12 y61 ff8 fsf fc0 sc0 ls0 ws0">Page 32</div><div class="t m0 x1b h12 y62 ff8 fsf fc0 sc0 ls0 ws0">Page 33</div><div class="t m0 x1b h12 y63 ff8 fsf fc0 sc0 ls0 ws0">Page 34</div><div class="t m0 x1b h12 y64 ff8 fsf fc0 sc0 ls0 ws0">Page 35</div><div class="t m0 x1b h12 y65 ff8 fsf fc0 sc0 ls0 ws0">Page 36</div><div class="t m0 x1b h12 y66 ff8 fsf fc0 sc0 ls0 ws0">Page 37</div><div class="t m0 x1b h12 y67 ff8 fsf fc0 sc0 ls0 ws0">Page 38</div><div class="t m0 x1b h12 y4d ff8 fsf fc0 sc0 ls0 ws0">Page 1</div><div class="t m0 x1b h12 y68 ff8 fsf fc0 sc0 ls0 ws0">Page 39</div><div class="t m0 x1b h12 y69 ff8 fsf fc0 sc0 ls0 ws0">Page 40</div><div class="t m0 x1b h12 y6a ff8 fsf fc0 sc0 ls0 ws0">Page 41</div><div class="t m0 x1b h12 y6b ff8 fsf fc0 sc0 ls0 ws0">Page 42</div><div class="t m0 x1b h12 y6c ff8 fsf fc0 sc0 ls0 ws0">Page 43</div><div class="t m0 x1b h12 y6d ff8 fsf fc0 sc0 ls0 ws0">Page 44</div><div class="t m0 x1b h12 y37 ff8 fsf fc0 sc0 ls0 ws0">Page 45</div><div class="t m0 x1b h12 y6e ff8 fsf fc0 sc0 ls0 ws0">Page 46</div><div class="t m0 x1b h12 y6f ff8 fsf fc0 sc0 ls0 ws0">Page 47</div><div class="t m0 x1b h12 y70 ff8 fsf fc0 sc0 ls0 ws0">Page 48</div><div class="t m0 x1b h12 y71 ff8 fsf fc0 sc0 ls0 ws0">Page 49</div><div class="t m0 x1b h12 y72 ff8 fsf fc0 sc0 ls0 ws0">Page 50</div><div class="t m0 x1b h12 y73 ff8 fsf fc0 sc0 ls0 ws0">Page 51</div><div class="t m0 x1b h12 y74 ff8 fsf fc0 sc0 ls0 ws0">Page 52</div><div class="t m0 x1b h12 y75 ff8 fsf fc0 sc0 ls0 ws0">Page 53</div><div class="t m0 x1d h13 y76 ff3 fs10 fc3 sc0 ls0 ws0">Note</div><div class="t m0 x1d h13 y77 ff3 fs10 fc4 sc0 ls0 ws0">Option</div><div class="t m0 x1d h13 y78 ff3 fs10 fc2 sc0 ls0 ws0">Description</div><div class="t m0 x1c h12 y45 ff8 fsf fc0 sc0 ls0 ws0">02.Revision History</div><div class="t m0 x1c h12 y46 ff8 fsf fc0 sc0 ls0 ws0">03.Block Diagram</div><div class="t m0 x1c h12 y47 ff8 fsf fc0 sc0 ls0 ws0">04.Power Tr<span class="_ _2"></span>ee</div><div class="t m0 x1c h12 y48 ff8 fsf fc0 sc0 ls0 ws0">05.Power S<span class="_ _2"></span>equence/IO Domain Map</div><div class="t m0 x1c h12 y4c ff8 fsf fc0 sc0 ls0 ws0">10.RK3588_<span class="_ _2"></span>Power/GND</div><div class="t m0 x1c h12 y4e ff8 fsf fc0 sc0 ls0 ws0">11.RK3588_<span class="_ _2"></span>OSC/PLL/PMUIO</div><div class="t m0 x1c h12 y50 ff8 fsf fc0 sc0 ls0 ws0">13.RK3588_<span class="_ _2"></span>Flash/SD Controller</div><div class="t m0 x1c h12 y4f ff8 fsf fc0 sc0 ls0 ws0">12.RK3588 <span class="_ _2"></span>DDR Contro<span class="_ _2"></span>ler</div><div class="t m0 x1c h12 y52 ff8 fsf fc0 sc0 ls0 ws0">15.RK3588_<span class="_ _2"></span>SARADC<span class="_ _2"></span>/1.8V Only GPIO</div><div class="t m0 x1c h12 y51 ff8 fsf fc0 sc0 ls0 ws0">14.RK3588_<span class="_ _2"></span>USB30/USB20<span class="_ _2"></span>_Ctrl</div><div class="t m0 x1c h12 y53 ff8 fsf fc0 sc0 ls0 ws0">16.RK3588_<span class="_ _2"></span>MIPI Interface</div><div class="t m0 x1c h12 y54 ff8 fsf fc0 sc0 ls0 ws0">17.RK3588_<span class="_ _2"></span>HDMI/eDP Interface</div><div class="t m0 x1c h12 y55 ff8 fsf fc0 sc0 ls0 ws0">18.RK3588_<span class="_ _2"></span>PCIE30/PCIE20/SATA30</div><div class="t m0 x1c h12 y57 ff8 fsf fc0 sc0 ls0 ws0">20.Power_DC I<span class="_ _2"></span>N</div><div class="t m0 x1c h12 y56 ff8 fsf fc0 sc0 ls0 ws0">19.RK3588_<span class="_ _2"></span>1.8V/ 3.3<span class="_ _2"></span>V GPIO</div><div class="t m0 x1c h12 y59 ff8 fsf fc0 sc0 ls0 ws0">25.USB2/USB3<span class="_ _2"></span>/TypeC Port</div><div class="t m0 x1c h12 y1a ff8 fsf fc0 sc0 ls0 ws0">21.Power-PMIC_RK806<span class="_ _2"></span>-1</div><div class="t m0 x1c h12 y5a ff8 fsf fc0 sc0 ls0 ws0">38.DRAM-LPDDR4X_200P_<span class="_ _2"></span>1X32bit</div><div class="t m0 x1c h12 y5b ff8 fsf fc0 sc0 ls0 ws0">40.Flash-eMMC Flash</div><div class="t m0 x1c h12 y5c ff8 fsf fc0 sc0 ls0 ws0">43.Flash-SPI FLASH(Option)</div><div class="t m0 x1c h12 y5d ff8 fsf fc0 sc0 ls0 ws0">47.VI-Camera_MIPI-CSI</div><div class="t m0 x1c h12 y60 ff8 fsf fc0 sc0 ls0 ws0">55.VO-HDMI1.4 TX(MIPI to HDMI)</div><div class="t m0 x1c h12 yb ff8 fsf fc0 sc0 ls0 ws0">67.Ethernet-GEPHY<span class="_ _6"></span>_RGMII0</div><div class="t m0 x1c h12 y62 ff8 fsf fc0 sc0 ls0 ws0">70.Audio Port</div><div class="t m0 x1c h12 y61 ff8 fsf fc0 sc0 ls0 ws0">68.Ethernet-GEPHY<span class="_ _6"></span>_RGMII1</div><div class="t m0 x1c h12 y64 ff8 fsf fc0 sc0 ls0 ws0">83.SATA-SATA <span class="_ _2"></span>PM1</div><div class="t m0 x1c h12 y66 ff8 fsf fc0 sc0 ls0 ws0">90.IR Rec<span class="_ _2"></span>eiver/LED</div><div class="t m0 x1c h12 y67 ff8 fsf fc0 sc0 ls0 ws0">91.Debug UART/JTAG</div><div class="t m0 x1c h12 y6a ff8 fsf fc0 sc0 ls0 ws0">95.RS48<span class="_ _2"></span>5/RS232</div><div class="t m0 x1c h12 y6c ff8 fsf fc0 sc0 ls0 ws0">99.Mark/Hole/Heatsink</div><div class="t m0 x1c h12 y58 ff8 fsf fc0 sc0 ls0 ws0">22.Power_Ext Discret<span class="_ _2"></span>e/RTC IC</div><div class="t m0 x1c h12 y5e ff8 fsf fc0 sc0 ls0 ws0">50.VO-HDMI2.1 TX</div><div class="t m0 x1c h12 y65 ff8 fsf fc0 sc0 ls0 ws0">84.PCIE-PCIE3.0_1x4Lanes_RC_6<span class="_ _2"></span>4P</div><div class="t m0 x1c h12 y5f ff8 fsf fc0 sc0 ls0 ws0">51.VO-HDMI2.0 TX(DP to HDMI)</div><div class="t m0 x1c h12 y6b ff8 fsf fc0 sc0 ls0 ws0">98.Power Test</div><div class="t m0 x1c h12 y69 ff8 fsf fc0 sc0 ls0 ws0">93.HW_ID</div><div class="t m0 x1c h12 y68 ff8 fsf fc0 sc0 ls0 ws0">92.KEY</div><div class="t m0 x1c h12 y63 ff8 fsf fc0 sc0 ls0 ws0">82.SATA-SATA <span class="_ _2"></span>PM0</div><div class="t m0 x1c h12 y49 ff8 fsf fc0 sc0 ls0 ws0">06.Lower-Speed<span class="_ _2"></span> Bus Map</div><div class="t m0 x1c h12 y4a ff8 fsf fc0 sc0 ls0 ws0">07.USB/DP Configure Map</div><div class="t m0 x1c h12 y4b ff8 fsf fc0 sc0 ls0 ws0">08.PCIE Fun Map</div><div class="t m4 x1e h14 y79 ff5 fs11 fc0 sc0 ls0 ws0">Proj<span class="_ _6"></span>ect:</div><div class="t m0 x1e h15 y7a ff5 fs12 fc0 sc0 ls0 ws0">File:</div><div class="t m5 x1e h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Date:</div><div class="t m6 x1f h17 y7c ff1 fs14 fc0 sc0 ls0 ws0">Rockchip Electronics <span class="_ _2"></span>Co., Ltd</div><div class="t m5 x1e h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m5 x20 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Rev:</div><div class="t m5 x20 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">Sheet:<span class="_ _7"> </span> of</div><div class="t m5 x12 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m5 x21 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Tuesday, D<span class="_ _2"></span>ecember 14, 2021</div><div class="t m4 x21 h14 y7f ff5 fs11 fc0 sc0 ls0 ws0">01.I<span class="_ _6"></span>ndex <span class="_ _6"></span>and No<span class="_ _6"></span>tes</div><div class="t m4 x21 h14 y80 ff5 fs11 fc0 sc0 ls0 ws0">RK_NVR_DE<span class="_ _6"></span>M<span class="_ _6"></span>O1_RK35<span class="_ _6"></span>88_LP4/<span class="_ _6"></span>4x_V21</div><div class="t m5 x21 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m5 x22 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">2<span class="_ _8"> </span>43</div><div class="t m5 x23 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x24 h18 y81 ff1 fs15 fc0 sc0 ls0 ws0">Default</div><div class="t m4 x1e h14 y79 ff5 fs11 fc0 sc0 ls0 ws0">Proj<span class="_ _6"></span>ect:</div><div class="t m0 x1e h15 y7a ff5 fs12 fc0 sc0 ls0 ws0">File:</div><div class="t m5 x1e h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Date:</div><div class="t m6 x1f h17 y7c ff1 fs14 fc0 sc0 ls0 ws0">Rockchip Electronics <span class="_ _2"></span>Co., Ltd</div><div class="t m5 x1e h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m5 x20 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Rev:</div><div class="t m5 x20 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">Sheet:<span class="_ _7"> </span> of</div><div class="t m5 x12 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m5 x21 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Tuesday, D<span class="_ _2"></span>ecember 14, 2021</div><div class="t m4 x21 h14 y7f ff5 fs11 fc0 sc0 ls0 ws0">01.I<span class="_ _6"></span>ndex <span class="_ _6"></span>and No<span class="_ _6"></span>tes</div><div class="t m4 x21 h14 y80 ff5 fs11 fc0 sc0 ls0 ws0">RK_NVR_DE<span class="_ _6"></span>M<span class="_ _6"></span>O1_RK35<span class="_ _6"></span>88_LP4/<span class="_ _6"></span>4x_V21</div><div class="t m5 x21 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m5 x22 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">2<span class="_ _8"> </span>43</div><div class="t m5 x23 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x24 h18 y81 ff1 fs15 fc0 sc0 ls0 ws0">Default</div><div class="t m4 x1e h14 y79 ff5 fs11 fc0 sc0 ls0 ws0">Proj<span class="_ _6"></span>ect:</div><div class="t m0 x1e h15 y7a ff5 fs12 fc0 sc0 ls0 ws0">File:</div><div class="t m5 x1e h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Date:</div><div class="t m6 x1f h17 y7c ff1 fs14 fc0 sc0 ls0 ws0">Rockchip Electronics <span class="_ _2"></span>Co., Ltd</div><div class="t m5 x1e h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m5 x20 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Rev:</div><div class="t m5 x20 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">Sheet:<span class="_ _7"> </span> of</div><div class="t m5 x12 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m5 x21 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">Tuesday, D<span class="_ _2"></span>ecember 14, 2021</div><div class="t m4 x21 h14 y7f ff5 fs11 fc0 sc0 ls0 ws0">01.I<span class="_ _6"></span>ndex <span class="_ _6"></span>and No<span class="_ _6"></span>tes</div><div class="t m4 x21 h14 y80 ff5 fs11 fc0 sc0 ls0 ws0">RK_NVR_DE<span class="_ _6"></span>M<span class="_ _6"></span>O1_RK35<span class="_ _6"></span>88_LP4/<span class="_ _6"></span>4x_V21</div><div class="t m5 x21 h16 y7d ff1 fs13 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m5 x22 h16 y7e ff1 fs13 fc0 sc0 ls0 ws0">2<span class="_ _8"> </span>43</div><div class="t m5 x23 h16 y7b ff1 fs13 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x24 h18 y81 ff1 fs15 fc0 sc0 ls0 ws0">Default</div></div><div class="pi" data-data='{"ctm":[1.140251,0.000000,0.000000,1.140251,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/85084630/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m0 x2 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">4</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">4</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m0 x3 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m0 x4 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m0 x4 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m0 x5 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1</div><div class="t m0 x5 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">1</div><div class="t m0 x6 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0">D<span class="_ _0"> </span>D</div><div class="t m0 x6 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0">C<span class="_ _0"> </span>C</div><div class="t m0 x6 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">B<span class="_ _1"> </span>B</div><div class="t m0 x6 h2 y6 ff1 fs0 fc0 sc0 ls0 ws0">A<span class="_ _1"> </span>A</div><div class="t m0 x9 h19 y82 ff3 fs16 fc0 sc0 ls0 ws0">Revision History</div><div class="t m0 x8 h1a y83 ff3 fs17 fc0 sc0 ls0 ws0">Version</div><div class="t m0 x8 h1a y84 ff8 fs17 fc0 sc0 ls0 ws0">V1.0</div><div class="t m0 x25 h1a y83 ff3 fs17 fc0 sc0 ls0 ws0">Date<span class="_ _9"> </span>By<span class="_ _a"> </span>Change D<span class="_ _2"></span>secription<span class="_ _b"> </span><span class="ff6">Approv<span class="_ _2"></span>ed</span></div><div class="t m0 x26 h1a y84 ff8 fs17 fc0 sc0 ls0 ws0">1:Revision preli<span class="_ _6"></span>minary ve<span class="_ _6"></span>rsion<span class="_ _c"></span>2021-09-24<span class="_ _d"> </span>Zhangdz</div><div class="t m0 x8 h1a y85 ff8 fs17 fc0 sc0 ls0 ws0">V2.0<span class="_ _e"> </span>2021-12-<span class="_ _2"></span>08<span class="_ _d"> </span>Z<span class="_ _6"></span>hangdz<span class="_ _f"> </span>1:Invalid version</div><div class="t m0 x8 h1a y86 ff8 fs17 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x26 h1a y87 ff8 fs17 fc0 sc0 ls0 ws0">1:Change conte<span class="_ _6"></span>nt Please Ref<span class="_ _6"></span>er to</div><div class="t m7 x27 h1b y87 ff7 fs18 fc0 sc0 ls0 ws0">：</div><div class="t m0 x26 h1a y88 ff8 fs17 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_<span class="_ _2"></span>LP4XD200<span class="_ _2"></span>P232SD8_<span class="_ _2"></span>V21_202<span class="_ _2"></span>112<span class="_ _2"></span>28_Modify_Notes_CN</div><div class="t m0 x28 h1a y86 ff8 fs17 fc0 sc0 ls0 ws0">Zhangdz<span class="_ _10"></span>2021-12-28</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Tuesday, December 28, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">02.Revision Hi<span class="_ _6"></span>story</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">3<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Tuesday, December 28, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">02.Revision Hi<span class="_ _6"></span>story</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">3<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div><div class="t m1 xb h9 y26 ff5 fs7 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 xb ha y27 ff5 fs8 fc0 sc0 ls0 ws0">File:</div><div class="t m2 xb hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 xc hc y29 ff1 fsa fc0 sc0 ls0 ws0">Rockchip Electronics Co.<span class="_ _2"></span>, Ltd</div><div class="t m2 xb hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Designed by:</div><div class="t m2 xd hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Rev:</div><div class="t m2 xd hb y2b ff1 fs9 fc0 sc0 ls0 ws0">Sheet:<span class="_ _3"> </span> of</div><div class="t m2 xe hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Reviewed by:</div><div class="t m2 xf hb y28 ff1 fs9 fc0 sc0 ls0 ws0">Tuesday, December 28, 2021</div><div class="t m1 xf h9 y2c ff5 fs7 fc0 sc0 ls0 ws0">02.Revision Hi<span class="_ _6"></span>story</div><div class="t m1 xf h9 y2d ff5 fs7 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x_V21</div><div class="t m2 xf hb y2a ff1 fs9 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t m2 x10 hb y2b ff1 fs9 fc0 sc0 ls0 ws0">3<span class="_ _4"> </span>43</div><div class="t m2 x11 hb y28 ff1 fs9 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x12 hd y2e ff1 fsb fc0 sc0 ls0 ws0">Default</div></div><div class="pi" data-data='{"ctm":[1.140251,0.000000,0.000000,1.140251,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/85084630/bg4.jpg"><div class="t m0 x13 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">5</div><div class="t m0 x13 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">5</div><div class="t m0 x29 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">4</div><div class="t m0 x29 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">4</div><div class="t m0 x3 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">3</div><div class="t m0 x3 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">3</div><div class="t m0 x2a h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">2</div><div class="t m0 x2a h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">2</div><div class="t m0 x2b h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">1</div><div class="t m0 x2b h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">1</div><div class="t m0 x2c h1c y8b ff1 fs19 fc0 sc0 ls0 ws0">D<span class="_ _11"> </span>D</div><div class="t m0 x2c h1c y8c ff1 fs19 fc0 sc0 ls0 ws0">C<span class="_ _11"> </span>C</div><div class="t m0 x2c h1c y8d ff1 fs19 fc0 sc0 ls0 ws0">B<span class="_ _11"> </span>B</div><div class="t m0 x2c h1c y8e ff1 fs19 fc0 sc0 ls0 ws0">A<span class="_ _11"> </span>A</div><div class="t m0 x2d h1d y8f ff3 fsb fc0 sc0 ls0 ws0">PCIE20</div><div class="t m0 x2d h1d y90 ff3 fsb fc0 sc0 ls0 ws0">/SATA30_<span class="_ _2"></span>1</div><div class="t m0 x2d h1d y64 ff3 fsb fc0 sc0 ls0 ws0">PCIE30 x2</div><div class="t m0 x2d h1d y91 ff3 fsb fc0 sc0 ls0 ws0">Port0</div><div class="t m8 x2e h1e y92 ff3 fs9 fc0 sc0 ls0 ws0">VCCIO1</div><div class="t m8 x2f h1e y92 ff3 fs9 fc0 sc0 ls0 ws0">VCCIO4</div><div class="t m0 x30 h1d y93 ff3 fsb fc0 sc0 ls0 ws0">EMMCIO</div><div class="t m8 x31 h1e y94 ff3 fs9 fc0 sc0 ls0 ws0">VCCIO6</div><div class="t m8 x32 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">MIPI </div><div class="t m8 x33 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">DPHY1 TX</div><div class="t m8 x34 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">CPHY1 TX</div><div class="t m8 x35 h1e y96 ff3 fs9 fc0 sc0 ls0 ws0">SARADC</div><div class="t m8 x36 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">TYPEC0</div><div class="t m8 x27 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">/DP0</div><div class="t m8 x37 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">TYPEC1</div><div class="t m8 x38 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">/DP1</div><div class="t m0 x39 h1d y98 ff3 fsb fc0 sc0 ls0 ws0">VCCIO2</div><div class="t m0 x3a h1d y99 ff3 fsb fc0 sc0 ls0 ws0">DDR</div><div class="t m0 x3a h1d y9a ff3 fsb fc0 sc0 ls0 ws0">CH1_C</div><div class="t m0 x3b h1d y99 ff3 fsb fc0 sc0 ls0 ws0">DDR</div><div class="t m0 x3b h1d y9a ff3 fsb fc0 sc0 ls0 ws0">CH1_D</div><div class="t m0 x3c h1d y9b ff3 fsb fc0 sc0 ls0 ws0">DDR</div><div class="t m0 x3c h1d y9c ff3 fsb fc0 sc0 ls0 ws0">CH0_B</div><div class="t m0 x3c h1d y9d ff3 fsb fc0 sc0 ls0 ws0">DDR</div><div class="t m0 x3c h1d y9e ff3 fsb fc0 sc0 ls0 ws0">CH0_A</div><div class="t m0 x3d h1d y9f ff3 fsb fc0 sc0 ls0 ws0">HDMI</div><div class="t m0 x3d h1d ya0 ff3 fsb fc0 sc0 ls0 ws0">/eDP</div><div class="t m0 x3d h1d ya1 ff3 fsb fc0 sc0 ls0 ws0">TX0</div><div class="t m0 x39 h1d y52 ff3 fsb fc0 sc0 ls0 ws0">HDMI</div><div class="t m0 x39 h1d ya2 ff3 fsb fc0 sc0 ls0 ws0">/eDP</div><div class="t m0 x39 h1d y53 ff3 fsb fc0 sc0 ls0 ws0">TX1</div><div class="t m0 x39 h1d ya3 ff3 fsb fc0 sc0 ls0 ws0">HDMI RX</div><div class="t m8 x3e h1e ya4 ff3 fs9 fc0 sc0 ls0 ws0">USB2</div><div class="t m8 x3f h1e ya4 ff3 fs9 fc0 sc0 ls0 ws0">HOST0/1</div><div class="t m8 x40 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">MIPI </div><div class="t m8 x41 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">DPHY0 TX</div><div class="t m8 x42 h1e y95 ff3 fs9 fc0 sc0 ls0 ws0">CPHY0 TX</div><div class="t m8 x43 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">MIPI </div><div class="t m8 x44 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">DPHY0 RX</div><div class="t m8 x45 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">CPHY0 RX</div><div class="t m8 x46 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">MIPI </div><div class="t m8 x47 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">DPHY1 RX</div><div class="t m8 x48 h1e y97 ff3 fs9 fc0 sc0 ls0 ws0">CPHY1 RX</div><div class="t m0 x2d h1d ya5 ff3 fsb fc0 sc0 ls0 ws0">MIPI </div><div class="t m0 x2d h1d y55 ff3 fsb fc0 sc0 ls0 ws0">CSI1 RX</div><div class="t m0 x2d h1d y52 ff3 fsb fc0 sc0 ls0 ws0">MIPI </div><div class="t m0 x2d h1d ya2 ff3 fsb fc0 sc0 ls0 ws0">CSI0 RX</div><div class="t m0 x30 h1d ya6 ff3 fsb fc0 sc0 ls0 ws0">VCCIO3</div><div class="t m0 x30 h1d ya7 ff3 fsb fc0 sc0 ls0 ws0">VCCIO5</div><div class="t m0 x30 h1d ya8 ff3 fsb fc0 sc0 ls0 ws0">PMUIO2</div><div class="t m0 x30 h1d y5b ff3 fsb fc0 sc0 ls0 ws0">OSC</div><div class="t m0 x2d h1d ya9 ff3 fsb fc0 sc0 ls0 ws0">PCIE20</div><div class="t m0 x2d h1d y62 ff3 fsb fc0 sc0 ls0 ws0">/SATA30_<span class="_ _2"></span>2</div><div class="t m0 x2d h1d y42 ff3 fsb fc0 sc0 ls0 ws0">USB30</div><div class="t m0 x2d h1d y63 ff3 fsb fc0 sc0 ls0 ws0">_2_SS</div><div class="t m0 x2d h1d yaa ff3 fsb fc0 sc0 ls0 ws0">PCIE20</div><div class="t m0 x2d h1d yab ff3 fsb fc0 sc0 ls0 ws0">/SATA30_<span class="_ _2"></span>0</div><div class="t m0 x49 h1f y5a ff3 fs1a fc0 sc0 ls0 ws0">Rockchip</div><div class="t m0 x49 h3 yac ff3 fs1 fc0 sc0 ls0 ws0">RK3588</div><div class="t m0 x49 h20 yad ff3 fs1b fc0 sc0 ls0 ws0">Quad A76 <span class="_ _2"></span>+ Quad A5<span class="_ _2"></span>5</div><div class="t m8 x4a h1e ya4 ff3 fs9 fc0 sc0 ls0 ws0">USB2</div><div class="t m8 x4b h1e ya4 ff3 fs9 fc0 sc0 ls0 ws0">OTG1/0</div><div class="t m0 x4c h21 y11 ff6 fs1c fc1 sc0 ls0 ws0">24MHz</div><div class="t m0 x30 h1d yae ff3 fsb fc0 sc0 ls0 ws0">PMUIO1</div><div class="t m0 x4d h1d yaa ff3 fsb fc0 sc0 ls0 ws0">LPDDR4 32bit</div><div class="t m0 x4d h1d yab ff3 fsb fc0 sc0 ls0 ws0">LPDDR4X 32bit</div><div class="t m0 x17 h20 yaf ff3 fs1b fc0 sc0 ls0 ws0">HDMI2.1 TX<span class="_ _12"></span>HDMI2.1 TX<span class="_ _12"></span>HDMI2.0 TX<span class="_ _13"></span>HDMI1.4 TX</div><div class="t m0 x48 h21 yb0 ff6 fs1c fc1 sc0 ls0 ws0">MIPI DPHY1 TX</div><div class="t m0 x4e h1d yb1 ff3 fsb fc0 sc0 ls0 ws0">MIPI DSI</div><div class="t m0 x4e h1d yb2 ff3 fsb fc0 sc0 ls0 ws0">to</div><div class="t m0 x4e h1d yb3 ff3 fsb fc0 sc0 ls0 ws0">HDMI</div><div class="t m0 x4f h1d y3 ff3 fsb fc0 sc0 ls0 ws0">DP</div><div class="t m0 x4f h1d yb4 ff3 fsb fc0 sc0 ls0 ws0">to</div><div class="t m0 x4f h1d yb5 ff3 fsb fc0 sc0 ls0 ws0">HDMI</div><div class="t m0 x50 h20 yaf ff3 fs1b fc0 sc0 ls0 ws0">TYPEC0</div><div class="t m0 x1 h1d yb6 ff3 fsb fc0 sc0 ls0 ws0">Giga PHY</div><div class="t m0 x51 h1d yb7 ff3 fsb fc0 sc0 ls0 ws0">RJ-45<span class="_ _14"></span>RJ-45</div><div class="t m0 x25 h1d yb6 ff3 fsb fc0 sc0 ls0 ws0">ACodec</div><div class="t m0 x52 h21 yb8 ff6 fs1c fc1 sc0 ls0 ws0">Line In</div><div class="t m0 x52 h21 yb9 ff6 fs1c fc1 sc0 ls0 ws0">Line Out</div><div class="t m0 x53 h21 yba ff6 fs1c fc1 sc0 ls0 ws0">Buzzer</div><div class="t m0 x54 h1d ybb ff3 fsb fc0 sc0 ls0 ws0">RS485</div><div class="t m0 x54 h1d ybc ff3 fsb fc0 sc0 ls0 ws0">RS232</div><div class="t m0 x1b h20 ybd ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 ybe ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 ybf ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc0 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc1 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x55 h21 yc2 ff6 fs1c fc1 sc0 ls0 ws0">SATA</div><div class="t m0 x55 h21 y93 ff6 fs1c fc1 sc0 ls0 ws0">PM</div><div class="t m0 x1b h20 yc3 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc4 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc5 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc6 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x1b h20 yc7 ff3 fs1b fc0 sc0 ls0 ws0">SATA3.0</div><div class="t m0 x55 h21 yc8 ff6 fs1c fc1 sc0 ls0 ws0">SATA</div><div class="t m0 x55 h21 y64 ff6 fs1c fc1 sc0 ls0 ws0">PM</div><div class="t m0 x56 h22 yc9 ff3 fs1d fc0 sc0 ls0 ws0">RK806-1</div><div class="t m0 x56 h22 yca ff3 fs1d fc0 sc0 ls0 ws0">+Discrete</div><div class="t m0 x56 h22 ycb ff3 fs1d fc0 sc0 ls0 ws0">Power</div><div class="t m0 x57 h21 ycc ff6 fs1c fc1 sc0 ls0 ws0">Power for RK3588</div><div class="t m0 xa h20 ycd ff3 fs1b fc1 sc0 ls0 ws0">12V</div><div class="t m0 xa h20 yce ff3 fs1b fc1 sc0 ls0 ws0">Adapter</div><div class="t m0 x58 h23 ycf ff3 fs1e fc0 sc0 ls0 ws0">eMMC5.1 </div><div class="t m0 x58 h23 yd0 ff3 fs1e fc0 sc0 ls0 ws0">or</div><div class="t m0 x58 h23 yd1 ff3 fs1e fc0 sc0 ls0 ws0">FSPI Flash</div><div class="t m0 x59 h21 yd2 ff6 fs1c fc1 sc0 ls0 ws0">PWM3_IR_M0</div><div class="t m0 x5a h20 yd3 ff3 fs1b fc0 sc0 ls0 ws0">IR Receiver</div><div class="t m0 x5b h20 yd4 ff3 fs1b fc0 sc0 ls0 ws0">Power LED<span class="_ _15"> </span>Ethernet LED<span class="_ _16"> </span>HDD LED<span class="_ _17"> </span>USB2.0 HO<span class="_ _2"></span>ST1<span class="_ _18"></span>TYPEC1_USB20_HO<span class="_ _2"></span>ST</div><div class="t m0 x5c h21 yd5 ff6 fs1c fc1 sc0 ls0 ws0">SARADC_IN0</div><div class="t m0 x5d h21 yc2 ff6 fs1c fc1 sc0 ls0 ws0">Recovery Key</div><div class="t m0 x5e h20 yd6 ff3 fs1b fc0 sc0 ls0 ws0">PCIe3.0 x4</div><div class="t m0 x5f h1d y41 ff3 fsb fc0 sc0 ls0 ws0">PCIE30 x2</div><div class="t m0 x5f h1d y67 ff3 fsb fc0 sc0 ls0 ws0">Port1</div><div class="t m0 x4c h21 y65 ff6 fs1c fc1 sc0 ls0 ws0">PCIe3.0 x2Lanes</div><div class="t m0 x60 h21 yd7 ff6 fs1c fc1 sc0 ls0 ws0">PCIe3.0 x2Lanes</div><div class="t m0 x61 h21 yd8 ff6 fs1c fc1 sc0 ls0 ws0">PCIe3.0 x4Lanes</div><div class="t m0 x62 h21 yc2 ff6 fs1c fc1 sc0 ls0 ws0">eMMC X8bit</div><div class="t m0 x62 h21 y15 ff6 fs1c fc1 sc0 ls0 ws0">or FSPI X4bit</div><div class="t m0 x63 h1d yd9 ff3 fsb fc0 sc0 ls0 ws0">LPDDR4 32bit</div><div class="t m0 x63 h1d yda ff3 fsb fc0 sc0 ls0 ws0">LPDDR4X 32bit</div><div class="t m0 x64 h1d ydb ff3 fsb fc0 sc0 ls0 ws0">Debug </div><div class="t m0 x64 h1d ydc ff3 fsb fc0 sc0 ls0 ws0">UART2</div><div class="t m0 x14 h21 ydd ff6 fs1c fc1 sc0 ls0 ws0">UART2</div><div class="t m0 x65 h1d yde ff3 fsb fc0 sc0 ls0 ws0">UART</div><div class="t m0 x66 h21 ydf ff6 fs1c fc1 sc0 ls0 ws0">UART5</div><div class="t m0 x65 h1d ya6 ff3 fsb fc0 sc0 ls0 ws0">JATG</div><div class="t m0 x66 h21 y1a ff6 fs1c fc1 sc0 ls0 ws0">JTAG</div><div class="t m0 x67 h21 yb0 ff6 fs1c fc1 sc0 ls0 ws0">DP1 x4</div><div class="t m9 x4b h24 ye0 ff6 fs1f fc1 sc0 ls0 ws0">TYPEC1_USB20_HOST</div><div class="t ma x68 h25 ye1 ff6 fs20 fc1 sc0 ls0 ws0">USB2_HOST0</div><div class="t ma x69 h25 ye1 ff6 fs20 fc1 sc0 ls0 ws0">USB2_HOST1</div><div class="t m0 x6a h21 ye2 ff6 fs1c fc1 sc0 ls0 ws0">TYPEC1_US<span class="_ _2"></span>B20_HOST<span class="_ _19"> </span>USB2_HOST<span class="_ _2"></span>1</div><div class="t ma x2e h25 ye3 ff6 fs20 fc1 sc0 ls0 ws0">I2S0</div><div class="t m0 x6b h21 ye4 ff6 fs1c fc1 sc0 ls0 ws0">I2S0<span class="_ _1a"> </span>I2C3</div><div class="t ma x50 h25 ye3 ff6 fs20 fc1 sc0 ls0 ws0">I2C3</div><div class="t ma x6c h25 ye5 ff6 fs20 fc1 sc0 ls0 ws0">SARADC</div><div class="t m0 x9 h21 ye6 ff6 fs1c fc1 sc0 ls0 ws0">RGMII0</div><div class="t m0 x1a h21 ye7 ff6 fs1c fc1 sc0 ls0 ws0">RGMII0</div><div class="t m0 x4c h21 ye8 ff6 fs1c fc1 sc0 ls0 ws0">SATA3.0_<span class="_ _2"></span>Port0</div><div class="t m0 x4c h21 ye9 ff6 fs1c fc1 sc0 ls0 ws0">SATA3.0_<span class="_ _2"></span>Port1</div><div class="t m0 x4c h21 yd ff6 fs1c fc1 sc0 ls0 ws0">USB30_2_<span class="_ _2"></span>SS</div><div class="t ma x6d h25 yea ff6 fs20 fc1 sc0 ls0 ws0">DP1 x4</div><div class="t m0 x6e h21 yeb ff6 fs1c fc1 sc0 ls0 ws0">TYPEC0/DP0</div><div class="t m0 x6f h26 yec ff9 fs1d fc5 sc0 ls0 ws0">SS</div><div class="t m0 x62 h20 yaf ff3 fs1b fc0 sc0 ls0 ws0">USB30_HOS<span class="_ _2"></span>T2</div><div class="t m0 x2 h21 yed ff6 fs1c fc1 sc0 ls0 ws0">USB30_2_<span class="_ _2"></span>SS</div><div class="t m0 x70 h1d yb6 ff3 fsb fc0 sc0 ls0 ws0">Giga PHY</div><div class="t m0 x1a h21 yee ff6 fs1c fc1 sc0 ls0 ws0">RGMII1</div><div class="t m0 x71 h21 ye6 ff6 fs1c fc1 sc0 ls0 ws0">RGMII1</div><div class="t m0 x72 h21 yed ff6 fs1c fc1 sc0 ls0 ws0">USB2_HOST0</div><div class="t m0 x5c h21 y5c ff6 fs1c fc1 sc0 ls0 ws0">RESET_L</div><div class="t m9 x5a h24 yef ff6 fs1f fc1 sc0 ls0 ws0">TYPEC0_USB20_OTG</div><div class="t m0 x50 h21 yf0 ff6 fs1c fc1 sc0 ls0 ws0">Download/adb Port</div><div class="t mb x4d h27 yf1 ffa fs21 fc1 sc0 ls0 ws0">Support:</div><div class="t mb x4d h27 yf2 ffa fs21 fc1 sc0 ls0 ws0">8K+4K+2K</div><div class="t mb x4d h27 yf3 ffa fs21 fc1 sc0 ls0 ws0">or</div><div class="t mb x4d h27 yf4 ffa fs21 fc1 sc0 ls0 ws0">4K+4K+4K+2K</div><div class="t m0 x73 h20 yaf ff3 fs1b fc0 sc0 ls0 ws0">MIPI CSI Connector</div><div class="t m0 x5c h1d yf5 ff3 fsb fc0 sc0 ls0 ws0">UART</div><div class="t m0 x5c h1d yf6 ff3 fsb fc0 sc0 ls0 ws0"><-></div><div class="t m0 x5c h1d yf7 ff3 fsb fc0 sc0 ls0 ws0">RS485</div><div class="t m0 x5c h1d yf8 ff3 fsb fc0 sc0 ls0 ws0">UART</div><div class="t m0 x5c h1d yf9 ff3 fsb fc0 sc0 ls0 ws0"><-></div><div class="t m0 x5c h1d yfa ff3 fsb fc0 sc0 ls0 ws0">RS232</div><div class="t ma x74 h25 yfb ff6 fs20 fc1 sc0 ls0 ws0">UART0_M2</div><div class="t ma x75 h25 yfb ff6 fs20 fc1 sc0 ls0 ws0">UART3_M2</div><div class="t m0 x76 h21 yfc ff6 fs1c fc1 sc0 ls0 ws0">UART0_M2</div><div class="t m0 x76 h21 yfd ff6 fs1c fc1 sc0 ls0 ws0">UART3_M2</div><div class="t m0 x49 h21 yfe ff6 fs1c fc1 sc0 ls0 ws0">TYPEC0_US<span class="_ _2"></span>B20_OTG</div><div class="t m0 x77 h21 yff ff6 fs1c fc1 sc0 ls0 ws0">With DP</div><div class="t m0 x78 h21 ye8 ff6 fs1c fc1 sc0 ls0 ws0">Reset Key</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 14,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">03.Block Diagram</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">4<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 14,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">03.Block Diagram</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">4<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 14,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">03.Block Diagram</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">4<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div></div><div class="pi" data-data='{"ctm":[1.140251,0.000000,0.000000,1.140251,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/85084630/bg5.jpg"><div class="t m0 x13 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">5</div><div class="t m0 x13 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">5</div><div class="t m0 x29 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">4</div><div class="t m0 x29 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">4</div><div class="t m0 x3 h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">3</div><div class="t m0 x3 h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">3</div><div class="t m0 x2a h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">2</div><div class="t m0 x2a h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">2</div><div class="t m0 x2b h1c y89 ff1 fs19 fc0 sc0 ls0 ws0">1</div><div class="t m0 x2b h1c y8a ff1 fs19 fc0 sc0 ls0 ws0">1</div><div class="t m0 x2c h1c y8b ff1 fs19 fc0 sc0 ls0 ws0">D<span class="_ _11"> </span>D</div><div class="t m0 x2c h1c y8c ff1 fs19 fc0 sc0 ls0 ws0">C<span class="_ _11"> </span>C</div><div class="t m0 x2c h1c y8d ff1 fs19 fc0 sc0 ls0 ws0">B<span class="_ _11"> </span>B</div><div class="t m0 x2c h1c y8e ff1 fs19 fc0 sc0 ls0 ws0">A<span class="_ _11"> </span>A</div><div class="t m0 x5e h3 y109 ff3 fs1 fc0 sc0 ls0 ws0">Power Tree</div><div class="t m0 x5e h1d yb7 ff3 fsb fc1 sc0 ls0 ws0">12V/3A</div><div class="t m0 x5e h1d y45 ff3 fsb fc1 sc0 ls0 ws0">Adapter</div><div class="t m0 x5e h1d y10a ff3 fsb fc1 sc0 ls0 ws0">Option1</div><div class="t m0 x73 h23 y10b ff8 fs1e fc3 sc0 ls0 ws0">3000mA</div><div class="t m0 x73 h23 y10c ff8 fs1e fc0 sc0 ls0 ws0">DC/DC</div><div class="t m0 x81 h1d y10d ff3 fsb fc1 sc0 ls0 ws0">ATX </div><div class="t m0 x81 h1d y10e ff3 fsb fc1 sc0 ls0 ws0">4Pin</div><div class="t m0 x81 h1d yff ff3 fsb fc1 sc0 ls0 ws0">Power</div><div class="t m0 x81 h1d y10f ff3 fsb fc1 sc0 ls0 ws0">Option2</div><div class="t m0 x82 h2d y110 ff3 fs26 fc0 sc0 ls0 ws0">VCC12V_DCIN</div><div class="t m0 x6b h2d y111 ff3 fs26 fc0 sc0 ls0 ws0">12V</div><div class="t m0 x74 h23 y112 ff8 fs1e fc3 sc0 ls0 ws0">3000mA<span class="_ _1c"></span><span class="fc0">DC/DC</span></div><div class="t m0 x83 h1d y113 ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_PCIE<span class="_ _1d"> </span><span class="fc3">Max:</span></div><div class="t mb x84 h27 y114 ffa fs21 fc3 sc0 ls0 ws0">Seq:0</div><div class="t m0 x85 h20 y115 ff3 fs1b fc1 sc0 ls0 ws0">Option</div><div class="t m0 x83 h1d y116 ff8 fsb fc1 sc0 ls0 ws0">USB2.0 HOS<span class="_ _2"></span>T1</div><div class="t m0 x83 h1d y117 ff8 fsb fc1 sc0 ls0 ws0">VCC5V_HDMI_TX0<span class="_ _2"></span>/1/2<span class="_ _1e"> </span><span class="fc3">Max:</span></div><div class="t m0 x39 h1d y116 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x83 h1d y118 ff8 fsb fc1 sc0 ls0 ws0">TYPEC1_USB20_<span class="_ _2"></span>HOST<span class="_ _1f"> </span><span class="fc3">Max:</span></div><div class="t m0 x83 h1d y119 ff8 fsb fc1 sc0 ls0 ws0">USB30_H<span class="_ _2"></span>OST2<span class="_ _20"> </span><span class="fc3">Max:</span></div><div class="t m0 x83 h1d y11a ff8 fsb fc1 sc0 ls0 ws0">TYPEC0<span class="_ _21"> </span><span class="fc3">Max:</span></div><div class="t m0 x83 h1d y11b ff8 fsb fc1 sc0 ls0 ws0">VCC5V_HDMI_TX3<span class="_ _22"> </span><span class="fc3">Max:</span></div><div class="t m0 x84 h2d y4b ff3 fs26 fc0 sc0 ls0 ws0">VCC5V0_SYS</div><div class="t m0 x39 h1d y11c ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _23"></span><span class="fc1">Camera Connector</span></div><div class="t m0 x39 h1d y11d ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _23"></span><span class="fc1">Camera Connector</span></div><div class="t m0 x2d h1d y11e ff8 fsb fc0 sc0 ls0 ws0">MOS<span class="_ _24"> </span><span class="fc1">VCC12V_PCIE30<span class="_ _25"> </span><span class="fc3">Max:</span></span></div><div class="t m0 x39 h1d y10d ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _23"></span><span class="fc1">FAN</span></div><div class="t m0 x86 h2e y11f ff4 fs26 fc3 sc0 ls0 ws0">Note:</div><div class="t mb x86 h27 y120 ffa fs21 fc0 sc0 ls0 ws0">With SATA,PCIe, the current is </div><div class="t mb x86 h27 y121 ffa fs21 fc0 sc0 ls0 ws0">estimated according to the </div><div class="t mb x86 h27 y122 ffa fs21 fc0 sc0 ls0 ws0">actual number of SATA,PCIe</div><div class="t m0 x87 h23 y10b ff8 fs1e fc3 sc0 ls0 ws0">8000mA</div><div class="t m0 x87 h23 y10c ff8 fs1e fc0 sc0 ls0 ws0">DC/DC</div><div class="t mb x82 h27 y114 ffa fs21 fc3 sc0 ls0 ws0">Seq:0</div><div class="t m0 x82 h2d y4b ff3 fs26 fc0 sc0 ls0 ws0">VCC4V0_SYS</div><div class="t m0 x39 h1d y123 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _23"></span><span class="fc1">FAN(Opt)</span></div><div class="t m0 x83 h1d y57 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_VDD_MIF</div><div class="t m0 x83 h1d ya7 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_VDD</div><div class="t m0 x83 h1d y98 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_VDD_MIF</div><div class="t m0 x83 h1d ya6 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_VDD</div><div class="t m0 x3d h2d y124 ff8 fs26 fc0 sc0 ls0 ws0">VCC_3<span class="_ _2"></span>V3</div><div class="t m0 x39 h1d ya7 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x39 h1d y57 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x39 h1d ya6 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x39 h1d y98 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x88 h1d y125 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_VDDQ_CKE</div><div class="t m0 x88 h1d ya8 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_VDDQ_CKE</div><div class="t mb x58 h27 y126 ffa fs21 fc0 sc0 ls0 ws0">Power on </div><div class="t mb x58 h27 y127 ffa fs21 fc0 sc0 ls0 ws0">Sequence</div><div class="t mb x89 h27 y128 ffa fs21 fc0 sc0 ls0 ws0">Seq:3</div><div class="t mb x89 h27 y129 ffa fs21 fc0 sc0 ls0 ws0">Seq:5</div><div class="t m0 x88 h1d y93 ff8 fsb fc1 sc0 ls0 ws0">LPDDR4/4x VDD2</div><div class="t m0 x88 h1d y98 ff8 fsb fc6 sc0 ls0 ws0">LPDDR4 VDDQ</div><div class="t mb x89 h27 y12a ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t m0 x8a h1d y12b ff3 fsb fc0 sc0 ls0 ws0">VCC1</div><div class="t m0 x6b h3 y12c ff3 fs1 fc0 sc0 ls0 ws0">RK806-1</div><div class="t m0 x8b h1d y12d ff3 fsb fc0 sc0 ls0 ws0">BUCK3</div><div class="t m0 x8b h1d y12e ff3 fsb fc0 sc0 ls0 ws0">5.0A max</div><div class="t m0 x8b h1d y12f ff3 fsb fc0 sc0 ls0 ws0">BUCK4</div><div class="t m0 x8b h1d y130 ff3 fsb fc0 sc0 ls0 ws0">5.0A max</div><div class="t m0 x8b h1d y131 ff3 fsb fc0 sc0 ls0 ws0">BUCK1</div><div class="t m0 x8b h1d y132 ff3 fsb fc0 sc0 ls0 ws0">6.5A max</div><div class="t m0 x8a h1d y133 ff3 fsb fc0 sc0 ls0 ws0">VCC2</div><div class="t m0 x8b h1d y134 ff3 fsb fc0 sc0 ls0 ws0">BUCK2</div><div class="t m0 x8b h1d y135 ff3 fsb fc0 sc0 ls0 ws0">5.0A max</div><div class="t m0 x8a h1d ya5 ff3 fsb fc0 sc0 ls0 ws0">VCC3</div><div class="t m0 x8a h1d y136 ff3 fsb fc0 sc0 ls0 ws0">VCC4</div><div class="t mb x89 h27 y137 ffa fs21 fc0 sc0 ls0 ws0">Seq:4</div><div class="t mb x89 h27 y138 ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t mb x89 h27 y139 ffa fs21 fc0 sc0 ls0 ws0">Seq:5</div><div class="t mb x89 h27 y13a ffa fs21 fc0 sc0 ls0 ws0">Seq:1</div><div class="t m0 x8a h1d y13b ff3 fsb fc0 sc0 ls0 ws0">VCC5</div><div class="t m0 x8b h1d y125 ff3 fsb fc0 sc0 ls0 ws0">BUCK7</div><div class="t m0 x8b h1d y13c ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x39 h1d y13d ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _26"></span><span class="ff3 fc0">BUCK8</span></div><div class="t m0 x8b h1d y13e ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x39 h1d y5b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8b h1d y57 ff3 fsb fc0 sc0 ls0 ws0">BUCK5</div><div class="t m0 x8b h1d y13f ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x8a h1d yde ff3 fsb fc0 sc0 ls0 ws0">VCC6</div><div class="t m0 x8b h1d y98 ff3 fsb fc0 sc0 ls0 ws0">BUCK6</div><div class="t m0 x8b h1d y140 ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x39 h1d y9d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8a h1d y141 ff3 fsb fc0 sc0 ls0 ws0">VCC7</div><div class="t m0 x8a h1d y142 ff3 fsb fc0 sc0 ls0 ws0">VCC8</div><div class="t mb x89 h27 y143 ffa fs21 fc0 sc0 ls0 ws0">Seq:6</div><div class="t m0 x39 h1d yae ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8b h1d y9d ff3 fsb fc0 sc0 ls0 ws0">BUCK9</div><div class="t m0 x8b h1d y9e ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x39 h1d y144 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8a h1d y145 ff3 fsb fc0 sc0 ls0 ws0">VCC9</div><div class="t mb x89 h27 y146 ffa fs21 fc0 sc0 ls0 ws0">Seq:3</div><div class="t m0 x8b h1d y144 ff3 fsb fc0 sc0 ls0 ws0">BUCK10</div><div class="t m0 x8b h1d y147 ff3 fsb fc0 sc0 ls0 ws0">2.5A max</div><div class="t m0 x8a h1d y148 ff3 fsb fc0 sc0 ls0 ws0">VCC10</div><div class="t mb x89 h27 y149 ffa fs21 fc0 sc0 ls0 ws0">Seq:3</div><div class="t mb x89 h27 y14a ffa fs21 fc0 sc0 ls0 ws0">Seq:3</div><div class="t mb x89 h27 y14b ffa fs21 fc0 sc0 ls0 ws0">Seq:4</div><div class="t m0 x8b h1d y14c ff3 fsb fc0 sc0 ls0 ws0">PLDO1</div><div class="t m0 x8b h1d y14d ff3 fsb fc0 sc0 ls0 ws0">500mA max</div><div class="t m0 x8a h1d y8f ff3 fsb fc0 sc0 ls0 ws0">VCC11</div><div class="t m0 x8b h1d y60 ff3 fsb fc0 sc0 ls0 ws0">PLDO2</div><div class="t m0 x8b h1d y14e ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t m0 x8b h1d y14f ff3 fsb fc0 sc0 ls0 ws0">PLDO3</div><div class="t m0 x8b h1d y150 ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t mb x89 h27 y151 ffa fs21 fc0 sc0 ls0 ws0">Seq:6</div><div class="t mb x89 h27 y152 ffa fs21 fc0 sc0 ls0 ws0">Seq:6</div><div class="t m0 x8a h1d y153 ff3 fsb fc0 sc0 ls0 ws0">VCC12</div><div class="t m0 x8b h1d y154 ff3 fsb fc0 sc0 ls0 ws0">PLDO4</div><div class="t m0 x8b h1d y155 ff3 fsb fc0 sc0 ls0 ws0">500mA max</div><div class="t m0 x8b h1d y156 ff3 fsb fc0 sc0 ls0 ws0">PLDO5</div><div class="t m0 x8b h1d y157 ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t mb x89 h27 y158 ffa fs21 fc0 sc0 ls0 ws0">Seq:3</div><div class="t m0 x8a h1d y159 ff3 fsb fc0 sc0 ls0 ws0">VCCA</div><div class="t m0 x8b h1d y15a ff3 fsb fc0 sc0 ls0 ws0">PLDO6</div><div class="t m0 x8b h1d y15b ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t mb x89 h27 y15c ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t mb x89 h27 y15d ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t mb x89 h27 y15e ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t m0 x8b h1d y15f ff3 fsb fc0 sc0 ls0 ws0">NLDO1</div><div class="t m0 x8b h1d y160 ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t m0 x8a h1d y161 ff3 fsb fc0 sc0 ls0 ws0">VCC13</div><div class="t m0 x8b h1d y162 ff3 fsb fc0 sc0 ls0 ws0">NLDO2</div><div class="t m0 x8b h1d y163 ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t m0 x8b h1d y69 ff3 fsb fc0 sc0 ls0 ws0">NLDO3</div><div class="t m0 x8b h1d y164 ff3 fsb fc0 sc0 ls0 ws0">500mA max</div><div class="t mb x89 h27 y165 ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t mb x89 h27 y166 ffa fs21 fc0 sc0 ls0 ws0">Seq:2</div><div class="t m0 x8a h1d y167 ff3 fsb fc0 sc0 ls0 ws0">VCC14</div><div class="t m0 x8b h1d y168 ff3 fsb fc0 sc0 ls0 ws0">NLDO4</div><div class="t m0 x8b h1d y169 ff3 fsb fc0 sc0 ls0 ws0">500mA max</div><div class="t m0 x8b h1d y16a ff3 fsb fc0 sc0 ls0 ws0">NLDO5</div><div class="t m0 x8b h1d y16b ff3 fsb fc0 sc0 ls0 ws0">300mA max</div><div class="t m0 x87 h1d y16c ff3 fsb fc0 sc0 ls0 ws0">RK860-2 ,6A</div><div class="t mb x57 h27 y16d ffa fs21 fc0 sc0 ls0 ws0">EN<span class="_ _27"></span>VCC_3V3</div><div class="t mb x89 h27 y16e ffa fs21 fc0 sc0 ls0 ws0">Seq:6A</div><div class="t m0 x8c h1d y5b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x87 h1d y16f ff3 fsb fc0 sc0 ls0 ws0">RK860-3 ,6A</div><div class="t m0 x8c h1d y9d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d yae ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y144 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y170 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y13d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d ya8 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t mb x57 h27 y171 ffa fs21 fc0 sc0 ls0 ws0">EN<span class="_ _27"></span>VCC_3V3</div><div class="t mb x89 h27 y172 ffa fs21 fc0 sc0 ls0 ws0">Seq:6A</div><div class="t m0 x8c h1d y125 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y93 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y98 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d ya6 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d y57 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8c h1d ya7 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x48 h2d y173 ff8 fs26 fc0 sc0 ls0 ws0">VDDQ_DDR</div><div class="t m0 x8d h2d y174 ff8 fs26 fc0 sc0 ls0 ws0">VCC_1<span class="_ _2"></span>V8</div><div class="t m0 x8e h1d y175 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y60 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y176 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y14f ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y177 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y154 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y5f ff8 fs26 fc0 sc0 ls0 ws0">VCCA_1<span class="_ _2"></span>V8</div><div class="t m0 x2 h2d y178 ff8 fs26 fc0 sc0 ls0 ws0">VCCA1V<span class="_ _2"></span>8_IMAGE</div><div class="t m0 x2 h2d y179 ff8 fs26 fc0 sc0 ls0 ws0">VCCA1V<span class="_ _2"></span>2_IMAGE</div><div class="t m0 x2 h2d y17a ff8 fs26 fc0 sc0 ls0 ws0">VCCA_3<span class="_ _2"></span>V3</div><div class="t m0 x2 h2d y17b ff8 fs26 fc0 sc0 ls0 ws0">VCCIO_SD</div><div class="t m0 x2 h2d y17c ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>75_PMU</div><div class="t m0 x42 h1d y176 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y68 ff8 fs26 fc0 sc0 ls0 ws0">VDDA_DD<span class="_ _2"></span>R_PLL</div><div class="t m0 x2 h2d y17d ff8 fs26 fc0 sc0 ls0 ws0">VCCA1V<span class="_ _2"></span>8_PLDO6</div><div class="t m0 x42 h1d y177 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y17e ff8 fs26 fc0 sc0 ls0 ws0">VDDA0V7<span class="_ _2"></span>5_IMAGE</div><div class="t m0 x2 h2d y17f ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>85</div><div class="t m0 x8f h1d y176 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y154 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y177 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y64 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y15a ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y99 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _28"></span><span class="fc0">PCIE20_SATA<span class="_ _2"></span>30_USB30<span class="_ _2"></span>_2_AV<span class="_ _2"></span>DD_1V8</span></div><div class="t m0 x8f h1d y156 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y180 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y60 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y175 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8f h1d y14f ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x42 h1d y99 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _29"></span><span class="fc1">VDD1_1V8_<span class="_ _2"></span>DDR(Opt)</span></div><div class="t m0 x90 h1d y57 ff8 fsb fc1 sc0 ls0 ws0">VDD1_1V8_<span class="_ _2"></span>DDR</div><div class="t m0 x42 h1d y64 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _29"></span><span class="fc7">NC</span></div><div class="t m0 x8e h1d y15f ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y99 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x42 h1d y162 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x42 h1d y181 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x91 h2d y178 ff8 fs26 fc0 sc0 ls0 ws0">VCCA1V<span class="_ _2"></span>8_IMAGE</div><div class="t m0 x92 h2d y5f ff8 fs26 fc0 sc0 ls0 ws0">VCCA_1<span class="_ _2"></span>V8</div><div class="t m0 x8e h1d y181 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y162 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y182 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y69 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x42 h2d y17c ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>75_PMU</div><div class="t m0 x93 h2d y17f ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>85</div><div class="t m0 x8e h1d y183 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y184 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y16c ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y37 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y185 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y186 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y64 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y156 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2a"></span><span class="fc0">MIPI_D/C_PHY1_VDD_1V<span class="_ _2"></span>8</span></div><div class="t mb x89 h27 y187 ffa fs21 fc0 sc0 ls0 ws0">Seq:6</div><div class="t m0 x2 h1d y188 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h1d y189 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h1d ydb ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y18a ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y18b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8e h1d y18c ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x42 h2d y18d ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>75</div><div class="t m0 x42 h2d y17e ff8 fs26 fc0 sc0 ls0 ws0">VDDA0V7<span class="_ _2"></span>5_IMAGE</div><div class="t m0 x90 h1d ya7 ff8 fsb fc1 sc0 ls0 ws0">eMMC VCCQ</div><div class="t m0 x8c h1d y12f ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2b"></span><span class="fc1">SPI FLASH VCC</span></div><div class="t m0 x8c h1d y18e ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2b"></span><span class="fc1">Camera Connector</span></div><div class="t m0 x2d h1d y16c ff8 fsb fc0 sc0 ls0 ws0">VDDCPU_BIG0<span class="_ _2c"> </span>VDDCPU_BIG0_MEM</div><div class="t m0 x2d h1d y18a ff8 fsb fc0 sc0 ls0 ws0">VDDCPU_BIG1</div><div class="t m0 x2d h1d y18b ff8 fsb fc0 sc0 ls0 ws0">VDDCPU_BIG1_MEM</div><div class="t m0 x6a h1d y180 ff8 fsb fc0 sc0 ls0 ws0">OSC_1V8</div><div class="t m0 x83 h1d y99 ff8 fsb fc0 sc0 ls0 ws0">PLL_DVDD0V75</div><div class="t m0 x6a h1d y60 ff8 fsb fc0 sc0 ls0 ws0">PLL_AVDD1V8</div><div class="t m0 x90 h1d y12d ff8 fsb fc1 sc0 ls0 ws0">VCCIO_PHY0/1(Opt)<span class="_ _2d"> </span><span class="fc3">Max:</span></div><div class="t m0 x90 h1d y9f ff8 fsb fc1 sc0 ls0 ws0">ES8311 <span class="_ _2"></span>PVDD<span class="_ _3"> </span><span class="fc3">Max:</span></div><div class="t m0 x90 h1d ya6 ff8 fsb fc0 sc0 ls0 ws0">PMUIO1_1V8</div><div class="t m0 x83 h1d y15f ff8 fsb fc0 sc0 ls0 ws0">PMU_0V75</div><div class="t m0 x90 h1d y98 ff8 fsb fc0 sc0 ls0 ws0">PMUIO2_1V8</div><div class="t m0 x2d h1d y162 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_PLL_DVDD</div><div class="t m0 x6a h1d y176 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_PLL_AVDD1V8</div><div class="t m0 x83 h1d y9d ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_VDDQ_CK</div><div class="t m0 x83 h1d y144 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH0_VDDQ</div><div class="t m0 x8d h1d y125 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8d h1d ya8 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8d h1d y13d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8d h1d y5b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2d h1d y181 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_PLL_DVDD</div><div class="t m0 x6a h1d y154 ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_PLL_AVDD1V8</div><div class="t m0 x8d h1d y9d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8d h1d y93 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x83 h1d y5b ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_VDDQ_CK</div><div class="t m0 x8d h1d y98 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x83 h1d yae ff8 fsb fc0 sc0 ls0 ws0">DDR_CH1_VDDQ</div><div class="t m0 x8d h1d ya6 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x90 h1d y93 ff8 fsb fc0 sc0 ls0 ws0">EMMCIO_1V8</div><div class="t m0 x90 h1d ya8 ff8 fsb fc0 sc0 ls0 ws0">VCCIO2_1V8</div><div class="t m0 x8d h1d y57 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x8d h1d ya7 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x6a h1d y125 ff8 fsb fc1 sc0 ls0 ws0">VCC_RTC</div><div class="t m0 x6a h1d y177 ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP0_VDDH_1<span class="_ _2"></span>V8</div><div class="t m0 x6a h1d y93 ff8 fsb fc1 sc0 ls0 ws0">eMMC VCC</div><div class="t m0 x6a h1d y98 ff8 fsb fc1 sc0 ls0 ws0">Camera Connector</div><div class="t m0 x6a h1d ya6 ff8 fsb fc1 sc0 ls0 ws0">DP To HDMI(3.3V)</div><div class="t m0 x6a h1d y57 ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_VGA</div><div class="t m0 x6a h1d ya7 ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_PHY0/1</div><div class="t m0 x6a h1d ya8 ff8 fsb fc0 sc0 ls0 ws0">PMUIO2</div><div class="t m0 x6a h1d y13d ff8 fsb fc0 sc0 ls0 ws0">VCCIO2</div><div class="t m0 x6a h1d y9d ff8 fsb fc0 sc0 ls0 ws0">USB20_A<span class="_ _2"></span>VDD_3V3</div><div class="t m0 x6a h1d y156 ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP1_VDDH_1<span class="_ _2"></span>V8</div><div class="t m0 x6a h1d y5b ff8 fsb fc0 sc0 ls0 ws0">VCCIO6</div><div class="t m0 x83 h1d y184 ff8 fsb fc0 sc0 ls0 ws0">USB20_DV<span class="_ _2"></span>DD_0V75</div><div class="t m0 x6a h1d y175 ff8 fsb fc0 sc0 ls0 ws0">USB20_A<span class="_ _2"></span>VDD_1V8</div><div class="t m0 x8d h1d y12f ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2d h1d y177 ff8 fsb fc1 sc0 ls0 ws0">ES8311 <span class="_ _2"></span>AVDD/DVDD</div><div class="t m0 x90 h1d y125 ff8 fsb fc0 sc0 ls0 ws0">VCCIO1_1V8</div><div class="t m0 x8d h1d y18e ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x90 h1d y13d ff8 fsb fc0 sc0 ls0 ws0">VCCIO3_1V8</div><div class="t m0 x6a h1d y14f ff8 fsb fc0 sc0 ls0 ws0">SARADC_AVDD_1V<span class="_ _2"></span>8</div><div class="t m0 x6a h1d y12f ff8 fsb fc1 sc0 ls0 ws0">BEEP</div><div class="t m0 x6a h1d y18e ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_SATA<span class="_ _2"></span>PM0/1</div><div class="t m0 x83 h1d y183 ff8 fsb fc0 sc0 ls0 ws0">OTP_VDDOTP_0V75</div><div class="t m0 x8d h1d y12d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x83 h1d y18a ff8 fsb fc0 sc0 ls0 ws0">MIPI_D/C_PHY1_VDD</div><div class="t m0 x2d h1d y176 ff8 fsb fc0 sc0 ls0 ws0">MIPI_D/C_PHY1_VDD_1V<span class="_ _2"></span>2</div><div class="t m0 x48 h2d y18f ff8 fs26 fc0 sc0 ls0 ws0">VCC_3<span class="_ _2"></span>V3</div><div class="t m0 x83 h1d y37 ff8 fsb fc0 sc0 ls0 ws0">MIPI_CSI0_AVCC0V<span class="_ _2"></span>75</div><div class="t m0 x83 h1d y60 ff8 fsb fc0 sc0 ls0 ws0">MIPI_CSI0_AVCC1V<span class="_ _2"></span>8</div><div class="t m0 x83 h1d y16c ff8 fsb fc0 sc0 ls0 ws0">MIPI_CSI1_AVCC0V<span class="_ _2"></span>75</div><div class="t m0 x83 h1d y175 ff8 fsb fc0 sc0 ls0 ws0">MIPI_CSI1_AVCC1V<span class="_ _2"></span>8</div><div class="t m0 x83 h1d y162 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX0_V<span class="_ _2"></span>DD_0V75</div><div class="t m0 x83 h1d y181 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX0_A<span class="_ _2"></span>VDD_0V75</div><div class="t m0 x83 h1d y14f ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX0_V<span class="_ _2"></span>DD_IO_1V8</div><div class="t m0 x83 h1d y176 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX0_V<span class="_ _2"></span>DD_CMN_1V8</div><div class="t m0 x83 h1d y69 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX1_V<span class="_ _2"></span>DD_0V75</div><div class="t m0 x83 h1d y182 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX1_A<span class="_ _2"></span>VDD_0V75</div><div class="t m0 x83 h1d y154 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX1_V<span class="_ _2"></span>DD_IO_1V8</div><div class="t m0 x83 h1d y177 ff8 fsb fc0 sc0 ls0 ws0">HDMI/EDP_TX1_V<span class="_ _2"></span>DD_CMN_1V8</div><div class="t m0 x6a h1d y64 ff8 fsb fc0 sc0 ls0 ws0">PCIE20_SATA<span class="_ _2"></span>30_0_A<span class="_ _2"></span>VDD_1V8</div><div class="t m0 x6a h1d y15a ff8 fsb fc0 sc0 ls0 ws0">PCIE20_SATA<span class="_ _2"></span>30_1_A<span class="_ _2"></span>VDD_1V8</div><div class="t m0 x6a h1d y16a ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP0_VDD_0V85</div><div class="t m0 x6a h1d y190 ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP0_VDDA_0V<span class="_ _2"></span>85</div><div class="t m0 x6a h1d y183 ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP1_VDDA_0V<span class="_ _2"></span>85</div><div class="t m0 x6a h1d y184 ff8 fsb fc0 sc0 ls0 ws0">TYPEC0_DP1_VDD_0V85</div><div class="t m0 x6a h1d y37 ff8 fsb fc0 sc0 ls0 ws0">PCIE20_SATA<span class="_ _2"></span>30_0_A<span class="_ _2"></span>VDD_0V85</div><div class="t m0 x6a h1d y16c ff8 fsb fc0 sc0 ls0 ws0">PCIE20_SATA<span class="_ _2"></span>30_1_A<span class="_ _2"></span>VDD_0V85</div><div class="t m0 x6a h1d y186 ff8 fsb fc0 sc0 ls0 ws0">PCIE20_SATA<span class="_ _2"></span>30_USB30<span class="_ _2"></span>_2_AV<span class="_ _2"></span>DD_0V85<span class="_ _2e"></span>PCIE30_PORT0_AV<span class="_ _2"></span>DD0V75</div><div class="t m0 x6a h1d y15f ff8 fsb fc0 sc0 ls0 ws0">PCIE30_PORT0_AV<span class="_ _2"></span>DD1V8</div><div class="t m0 x83 h1d y185 ff8 fsb fc0 sc0 ls0 ws0">PCIE30_PORT1_AV<span class="_ _2"></span>DD0V75</div><div class="t m0 x6a h1d y191 ff8 fsb fc0 sc0 ls0 ws0">PCIE30_PORT1_AV<span class="_ _2"></span>DD1V8</div><div class="t m0 x90 h1d yae ff8 fsb fc0 sc0 ls0 ws0">VCCIO5_1V8</div><div class="t m0 x90 h1d y144 ff8 fsb fc0 sc0 ls0 ws0">VCCIO5</div><div class="t m0 x6a h1d y12d ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_IR</div><div class="t m0 x90 h1d y170 ff8 fsb fc0 sc0 ls0 ws0">VCCIO6_1V8</div><div class="t m0 x8d h1d y9f ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x90 h1d y5b ff8 fsb fc0 sc0 ls0 ws0">VCCIO4_1V8</div><div class="t m0 x90 h1d y9d ff8 fsb fc0 sc0 ls0 ws0">VCCIO4</div><div class="t m0 x6a h1d y9f ff8 fsb fc1 sc0 ls0 ws0">LED</div><div class="t m0 x8d h1d y134 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2b"></span><span class="fc1">FT232RL</span></div><div class="t m0 x8d h1d y52 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2b"></span><span class="fc1">SIT3232E</span></div><div class="t m0 x8d h1d y131 ff8 fsb fc3 sc0 ls0 ws0">Max:<span class="_ _2b"></span><span class="fc1">SIT3485E</span></div><div class="t m0 x2 h1d y192 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y193 ff8 fs26 fc0 sc0 ls0 ws0">VDD_CPU<span class="_ _2"></span>_BIG0</div><div class="t m0 x2 h2d y194 ff8 fs26 fc0 sc0 ls0 ws0">VDD_CPU<span class="_ _2"></span>_BIG1</div><div class="t m0 x48 h2d y195 ff8 fs26 fc0 sc0 ls0 ws0">VDD_DDR</div><div class="t m0 x2d h1d y52 ff8 fsb fc0 sc0 ls0 ws0">VDD_GPU<span class="_ _2f"> </span>VDD_GPU_MEM</div><div class="t m0 x2d h1d y9f ff8 fsb fc0 sc0 ls0 ws0">VDD_CPU_LIT<span class="_ _1b"> </span>VDD_CPU_LIT_MEM</div><div class="t m0 x2 h2d y196 ff8 fs26 fc0 sc0 ls0 ws0">VDD_LOGIC</div><div class="t m0 x2 h2d y197 ff8 fs26 fc0 sc0 ls0 ws0">VDD_CPU<span class="_ _2"></span>_LIT</div><div class="t m0 x2 h2d y174 ff8 fs26 fc0 sc0 ls0 ws0">VCC_1<span class="_ _2"></span>V8</div><div class="t m0 x2 h2d y195 ff8 fs26 fc0 sc0 ls0 ws0">VDD_DDR</div><div class="t m0 x2 h2d y198 ff8 fs26 fc0 sc0 ls0 ws0">VDD2_DD<span class="_ _2"></span>R</div><div class="t m0 x2 h2d y173 ff8 fs26 fc0 sc0 ls0 ws0">VDDQ_DDR</div><div class="t m0 x2 h2d y18f ff8 fs26 fc0 sc0 ls0 ws0">VCC_3<span class="_ _2"></span>V3</div><div class="t m0 x2 h2d y199 ff8 fs26 fc0 sc0 ls0 ws0">VCC_2<span class="_ _2"></span>V0_PLDO</div><div class="t m0 x2 h1d y19a ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h1d y19b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y19c ff8 fs26 fc0 sc0 ls0 ws0">VDD_GPU</div><div class="t m0 x94 h1d y52 ff8 fsb fc0 sc0 ls0 ws0">/</div><div class="t m0 x94 h1d y9f ff8 fsb fc0 sc0 ls0 ws0">/</div><div class="t m0 x2 h1d y19d ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x94 h1d y16c ff8 fsb fc0 sc0 ls0 ws0">/</div><div class="t m0 x2 h1d y19e ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h1d y18b ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y18d ff8 fs26 fc0 sc0 ls0 ws0">VDDA_0V<span class="_ _2"></span>75</div><div class="t m0 x83 h1d y13d ff8 fsb fc1 sc0 ls0 ws0">LPDDR4x VDDQ</div><div class="t m0 x95 h1d y98 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x95 h1d y93 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x95 h1d y125 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x95 h1d ya8 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x96 h2d y178 ff8 fs26 fc0 sc0 ls0 ws0">VCC_2<span class="_ _2"></span>V0_PLDO</div><div class="t m0 x96 h2d y68 ff8 fs26 fc0 sc0 ls0 ws0">VCC_1<span class="_ _2"></span>V1_NLDO</div><div class="t m0 x96 h2d y17f ff8 fs26 fc0 sc0 ls0 ws0">VCC_1<span class="_ _2"></span>V1_NLDO</div><div class="t m0 x2d h1d y19f ff8 fsb fc0 sc0 ls0 ws0">VDD_NPU<span class="_ _2f"> </span>VDD_NPU_MEM<span class="_ _30"></span>/</div><div class="t m0 x2 h2d y1a0 ff8 fs26 fc0 sc0 ls0 ws0">VDD_NPU</div><div class="t m0 x2 h1d y1a1 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2 h2d y56 ff8 fs26 fc0 sc0 ls0 ws0">VDD_VDENC</div><div class="t m0 x2 h1d ya3 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x2d h1d ya7 ff8 fsb fc0 sc0 ls0 ws0">VDD_VDENC<span class="_ _8"> </span>VDD_VDENC_MEM<span class="_ _31"></span>/</div><div class="t m0 x2d h1d y18e ff8 fsb fc0 sc0 ls0 ws0">VDD_LOGIC</div><div class="t m0 x83 h1d y1a2 ff8 fsb fc0 sc0 ls0 ws0">LDO , 500mA<span class="_ _32"> </span><span class="fc1">VCC3V3_PI6C<span class="_ _1d"> </span><span class="fc3">Max:</span></span></div><div class="t m0 x6a h1d y1a3 ff8 fsb fc1 sc0 ls0 ws0">DP To HDMI(1.0V)</div><div class="t m0 x83 h1d y1a4 ff8 fsb fc0 sc0 ls0 ws0">DC/DC , 2A<span class="_ _33"> </span><span class="fc1">VDD1V2_SA<span class="_ _2"></span>TAPM0/1<span class="_ _1b"> </span><span class="fc3">Max:</span></span></div><div class="t m0 x83 h1d y1a5 ff8 fsb fc0 sc0 ls0 ws0">DC/DC , 2A(Option)</div><div class="t m0 x83 h1d y1a3 ff8 fsb fc0 sc0 ls0 ws0">DC/DC , 2A</div><div class="t m0 x6a h1d y1a5 ff8 fsb fc1 sc0 ls0 ws0">VCC3V3_SATA<span class="_ _2"></span>PM0/1<span class="_ _34"> </span><span class="fc3">Max:</span></div><div class="t m0 x76 h1d y1a3 ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t m0 x6a h1d y1a6 ff8 fsb fc1 sc0 ls0 ws0">MIPI To HDMI(1.2V)<span class="_ _35"></span><span class="fc0">DC/DC , 2A<span class="_ _36"> </span><span class="fc3">Max:</span></span></div><div class="t m0 x87 h1d y19f ff3 fsb fc0 sc0 ls0 ws0">RK860-2 ,6A</div><div class="t mb x57 h27 y1a7 ffa fs21 fc0 sc0 ls0 ws0">EN<span class="_ _27"></span>VCC_3V3</div><div class="t mb x89 h27 y1a8 ffa fs21 fc0 sc0 ls0 ws0">Seq:6A</div><div class="t m0 x87 h1d y1a6 ff3 fsb fc0 sc0 ls0 ws0">EXT DC/DC ,2A</div><div class="t mb x57 h27 y1a9 ffa fs21 fc0 sc0 ls0 ws0">EN<span class="_ _37"></span>PMIC_EXT_EN_OUT</div><div class="t m0 x2 h1d y1aa ff8 fsb fc3 sc0 ls0 ws0">Max:</div><div class="t mb x89 h27 y1ab ffa fs21 fc3 sc0 ls0 ws0">Seq:0A</div><div class="t m0 x2 h2d y1ac ff8 fs26 fc0 sc0 ls0 ws0">VCC_1<span class="_ _2"></span>V1_NLDO</div><div class="t m0 x97 h2f y1ad ff4 fs27 fc0 sc0 ls0 ws0">The RK806<span class="_ _6"></span> LDO power dis<span class="_ _6"></span>tribution o<span class="_ _6"></span>f </div><div class="t m0 x97 h2f y1ae ff4 fs27 fc0 sc0 ls0 ws0">the refer<span class="_ _6"></span>ence schematic<span class="_ _6"></span>s is only s<span class="_ _6"></span>uitable </div><div class="t m0 x97 h2f y1af ff4 fs27 fc0 sc0 ls0 ws0">for the i<span class="_ _6"></span>nterface used <span class="_ _6"></span>in the refe<span class="_ _6"></span>rence schem<span class="_ _6"></span>atics. </div><div class="t m0 x97 h2f y1b0 ff4 fs27 fc0 sc0 ls0 ws0">If other <span class="_ _6"></span>interface func<span class="_ _6"></span>tions are t<span class="_ _6"></span>o be added <span class="_ _6"></span>to </div><div class="t m0 x97 h2f y1b1 ff4 fs27 fc0 sc0 ls0 ws0">the refer<span class="_ _6"></span>ence schematic<span class="_ _6"></span>s, the RK80<span class="_ _6"></span>6 LDO distr<span class="_ _6"></span>ibution </div><div class="t m0 x97 h2f y1b2 ff4 fs27 fc0 sc0 ls0 ws0">needs to <span class="_ _6"></span>be re evaluate<span class="_ _6"></span>d, otherwis<span class="_ _6"></span>e the added<span class="_ _6"></span> </div><div class="t m0 x97 h2f y1b3 ff4 fs27 fc0 sc0 ls0 ws0">functions<span class="_ _6"></span> may exceed th<span class="_ _6"></span>e maximum c<span class="_ _6"></span>urrent </div><div class="t m0 x97 h2f y1b4 ff4 fs27 fc0 sc0 ls0 ws0">provided <span class="_ _6"></span>by the LDO</div><div class="t m0 x97 h2f y1b5 ff4 fs27 fc3 sc0 ls0 ws0">Note:</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 21,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">04.Power Tree</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">5<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 21,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">04.Power Tree</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">5<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div><div class="t mc x79 h28 y100 ff5 fs22 fc0 sc0 ls0 ws0">Project:</div><div class="t m0 x79 h29 y101 ff5 fs23 fc0 sc0 ls0 ws0">File:</div><div class="t md x79 h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Date:</div><div class="t m3 x7a h2b y103 ff1 fs20 fc0 sc0 ls0 ws0">Rockchip Electronics Co<span class="_ _2"></span>., Ltd</div><div class="t md x79 h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Desi<span class="_ _2"></span>gned by:</div><div class="t md x7b h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Rev:</div><div class="t md x7b h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">Sheet:<span class="_ _8"> </span> of</div><div class="t md x7c h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Revi<span class="_ _2"></span>ewed by<span class="_ _2"></span>:</div><div class="t md x7d h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">Tuesday,<span class="_ _2"></span> Dec<span class="_ _2"></span>ember 21,<span class="_ _2"></span> 202<span class="_ _2"> </span>1</div><div class="t mc x7d h28 y106 ff5 fs22 fc0 sc0 ls0 ws0">04.Power Tree</div><div class="t mc x7d h28 y107 ff5 fs22 fc0 sc0 ls0 ws0">RK_NVR_DEMO1_RK3588_LP4/4x<span class="_ _6"></span>_V21</div><div class="t md x7d h2a y104 ff1 fs24 fc0 sc0 ls0 ws0">Zhangdz</div><div class="t md x7e h2a y105 ff1 fs24 fc0 sc0 ls0 ws0">5<span class="_ _1b"> </span>43</div><div class="t md x7f h2a y102 ff1 fs24 fc0 sc0 ls0 ws0">V2.1</div><div class="t m0 x80 h2c y108 ff1 fs25 fc0 sc0 ls0 ws0">Default</div></div><div class="pi" data-data='{"ctm":[1.140251,0.000000,0.000000,1.140251,0.000000,0.000000]}'></div></div>

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内容简介：04_Demo Reference Design.rar 04_Demo Reference Design 04_Demo Reference Design RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228.DSN RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228-162.DSN RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20211228_Modify_Notes_CN.pdf RK_NVR_DEMO1_RK3588_LP4XD200P232SD8_V21_20...

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