任意奇数分频电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div_odd IS
  PORT(
       ckin :IN STD_LOGIC;
       rst  :IN STD_LOGIC;
       ckout:OUT STD_LOGIC);
END div_odd;

ARCHITECTURE behavioral OF div_odd IS
 SIGNAL clk_tmp1 :STD_LOGIC;
 SIGNAL clk_tmp2 :STD_LOGIC;
 SIGNAL counter  :NATURAL RANGE 0 TO N;
BEGIN
  PROCESS(ckin)
 BEGIN
    IF(rst='0') THEN
      clk_tmp1<='0';
      counter<=0;
    ELSIF(ckin'EVENT AND ckin='1') THEN
       counter<=counter+1;
           IF(counter=(N-1)/2) THEN
                clk_tmp1<=NOT clk_tmp1;
             ELSIF(counter=N-1) THEN
              clk_tmp1<=NOT clk_tmp1;
                  counter<=0;
       END IF;