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ARM DDI 0439B (ID030210)

Cortex-M4

Revision r0p0

Technical Reference Manual

ID030210 Non-Confidential, Unrestricted Access

Cortex-M4

Technical Reference Manual

Release Information

The following changes have been made to this book.

Proprietary Notice

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Limited in the EU and other

countries, except as otherwise stated in this proprietary notice. Other brands and names mentioned herein may be the

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Neither the whole nor any part of the information contained in, or the product described in, this document may be

adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the

product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied

or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any

loss or damage arising from the use of any information in this document, or any error or omission in such information,

or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Some material in this document is based on IEEE 754-2008 IEEE Standard for Binary Floating-Point Arithmetic. The

IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license

restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this

document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final (information on a developed product).

Web Address

http://www.arm.com

Change History

Date Issue Confidentiality Change

22 December 2009 A Non-Confidential, Restricted Access First release for r0p0

02 March 2010 B Non-Confidential Second release for r0p0

ID030210 Non-Confidential, Unrestricted Access

Contents

Cortex-M4 Technical Reference Manual

Preface

About this book ........................................................................................................... ix

Feedback .................................................................................................................... xi

Chapter 1 Introduction

1.1 About the processor ................................................................................................. 1-2

1.2 Features ................................................................................................................... 1-3

1.3 Interfaces ................................................................................................................. 1-4

1.4 Configurable options ................................................................................................ 1-5

1.5 Product documentation ............................................................................................ 1-6

Chapter 2 Functional Description

2.1 About the functions .................................................................................................. 2-2

2.2 Interfaces ................................................................................................................. 2-5

Chapter 3 Programmers Model

3.1 About the programmers model ................................................................................ 3-2

3.2 Modes of operation and execution ........................................................................... 3-3

3.3 Instruction set summary ........................................................................................... 3-4

3.4 System address map ............................................................................................. 3-14

3.5 Write buffer ............................................................................................................ 3-17

3.6 Exclusive monitor ................................................................................................... 3-18

3.7 Bit-banding ............................................................................................................. 3-19

3.8 Processor core register summary .......................................................................... 3-21

3.9 Exceptions ............................................................................................................. 3-23

Chapter 4 System Control

4.1 About system control ............................................................................................... 4-2

Contents

ID030210 Non-Confidential, Unrestricted Access

4.2 Register summary .................................................................................................... 4-3

4.3 Register descriptions ............................................................................................... 4-5

Chapter 5 Memory Protection Unit

5.1 About the MPU ........................................................................................................ 5-2

5.2 MPU functional description ...................................................................................... 5-3

5.3 MPU programmers model ........................................................................................ 5-4

Chapter 6 Nested Vectored Interrupt Controller

6.1 About the NVIC ........................................................................................................ 6-2

6.2 NVIC functional description ..................................................................................... 6-3

6.3 NVIC programmers model ....................................................................................... 6-4

Chapter 7 Floating Point Unit

7.1 About the FPU ......................................................................................................... 7-2

7.2 FPU Functional Description ..................................................................................... 7-3

7.3 FPU Programmers Model ........................................................................................ 7-9

Chapter 8 Debug

8.1 About debug ............................................................................................................ 8-2

8.2 About the AHB-AP ................................................................................................... 8-6

8.3 About the Flash Patch and Breakpoint Unit (FPB) .................................................. 8-9

Chapter 9 Data Watchpoint and Trace Unit

9.1 About the DWT ........................................................................................................ 9-2

9.2 DWT functional description ...................................................................................... 9-3

9.3 DWT Programmers Model ....................................................................................... 9-4

Chapter 10 Instrumentation Trace Macrocell Unit

10.1 About the ITM ........................................................................................................ 10-2

10.2 ITM functional description ...................................................................................... 10-3

10.3 ITM programmers model ....................................................................................... 10-4

Chapter 11 Trace Port Interface Unit

11.1 About the Cortex-M4 TPIU .................................................................................... 11-2

11.2 TPIU functional description .................................................................................... 11-3

11.3 TPIU programmers model ..................................................................................... 11-5

Appendix A Revisions

Glossary

ID030210 Non-Confidential, Unrestricted Access

List of Tables

Cortex-M4 Technical Reference Manual

Change History ............................................................................................................................... ii

Table 3-1 Cortex-M4 instruction set summary ............................................................................................ 3-4

Table 3-2 Cortex-M4 DSP instruction set summary .................................................................................... 3-8

Table 3-3 Memory regions ........................................................................................................................ 3-14

Table 4-1 System control registers ............................................................................................................. 4-3

Table 4-2 ACTLR bit assignments .............................................................................................................. 4-5

Table 4-3 CPUID bit assignments ............................................................................................................... 4-6

Table 4-4 AFSR bit assignments ................................................................................................................ 4-7

Table 5-1 MPU registers ............................................................................................................................. 5-4

Table 6-1 NVIC registers ............................................................................................................................. 6-4

Table 6-2 ICTR bit assignments .................................................................................................................. 6-5

Table 7-1 FPU instruction set ...................................................................................................................... 7-4

Table 7-2 Default NaN values ..................................................................................................................... 7-6

Table 7-3 QNaN and SNaN handling .......................................................................................................... 7-7

Table 7-4 Cortex-M4F Floating Point system registers ............................................................................... 7-9

Table 8-1 Cortex-M4 ROM table identification values ................................................................................. 8-3

Table 8-2 Cortex-M4 ROM table components ............................................................................................ 8-3

Table 8-3 SCS identification values ............................................................................................................ 8-4

Table 8-4 Debug registers ........................................................................................................................... 8-5

Table 8-5 AHB-AP register summary .......................................................................................................... 8-6

Table 8-6 CSW bit assignments .................................................................................................................. 8-7

Table 8-7 FPB register summary .............................................................................................................. 8-10

Table 9-1 DWT register summary ............................................................................................................... 9-4

Table 10-1 ITM register summary ............................................................................................................... 10-4

Table 10-2 ITM_TPR bit assignments ......................................................................................................... 10-5

Table 11-1 TPIU registers ........................................................................................................................... 11-5

Table 11-2 TPIU_ACPR bit assignments .................................................................................................... 11-6

Table 11-3 TPIU_FFSR bit assignments .................................................................................................... 11-7

Table 11-4 TPIU_FFCR bit assignments .................................................................................................... 11-7

Table 11-5 TRIGGER bit assignments ........................................................................................................ 11-8