5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
/WR
/RD
/CS
1V8_OUT
/INT
XTLP
XTLN
1V8_OUT/RESET
VCC1V8
VCC3V3
VCC1A8
VCC3A3
RSET_BG
D15
D14
D13
D12
D11
D10
TXD0
D9
TXD1
OP_MODE0
D8
TXD2
OP_MODE1
D7
TXD3
OP_MODE2
D6
TX_EN
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
BIT16EN
A2
BRDY0J
A1
BRDY1J
A0
BRDY2J
BRDY3J
AVDD33
TX_CLK
RX_CLK
RXDV
RXD0
RXD1
RXD2
RXD3
COL
CRS
/FDX
PWFBOUT PWFBIN
TXOP
/LINKLED
/ACTLED
BIT16EN
/10_LED
/100_LED
/ACTLED
/100_LED
/RESET
VDD33
/FDX
RXIN
XTLP_P
RXD3
VDD33
AVDD33
PWFBIN
TXD0
/10_LED
TXD2
/COL_LED
XTLN_P
RXDV
TX_EN
TXD3
TXOP
PWFBOUT
RXD1
TXD1
RXD0
RXIP
CRS RXIN
RXIP
TX_CLK
TXON
TXON
/LINK_LED
COL
RX_CLK
RXD2
XTLN
XTLP
XTLN_P
XTLP_P
XTLN_P
XTLP_P
XTLP
OSC25I
OSC25I
XTLP_P
VDD33 VDD33
D[0..15]
A[0..9]
/WR
/RD
TXD[0..3]
GNDA
1V8A1V8D
1V8D3.3V1V8A3V3A
1V8D 3.3V
3V3A3.3V
GNDA
GNDA
3.3V
3.3V
GNDA
3V3A 3V3A
GNDA
GNDA
GNDA
3.3V
3.3V
3.3V
3.3V
3.3V
1.8V
GNDA
GNDA
Title
Size Document Number Re v
Date: Sheet
of
<Doc> 1.0
W5300 External PHY mode reference schematic
C
11Thursday, March 20, 2008
CONNECT TO CHASSIS GND
16BIT_EN
1-2 : 16 BIT DATA BUS
2-3 : 8 BIT DATA BUS
1608
CLOCK SOURCE OPTION
(You should adopt only one option.)
W5300 CLOCK : CRYSTAL(XTLP, XTLN), OSC(OSC25I)
PHY CLOCK : XTLP_P, XTLN_P
<OPTION1 : 2 CRYSTAL SOURCE> <OPTION2 : 1 Oscillator SOURCE> <OPTION3 : 1 CRYSTAL SOURCE>
[ Separate W5300 and PHY clock source ]
It is used for external PHY mode with
crystal clock (TEST_MODE[3:0]="0001").
[ Share W5300 and PHY clock source
with oscillator ]
It is used only in external PHY mode
with oscillator clock
(TEST_MODE[3:0]="0010").
In order to prevent the leakage current,
be sure to keep XTLP high and float
XTLN, and use 1.8v level oscillator.
[ Share W5300 and PHY clock source
with crystal ]
25MHz parallel-resonant crystal is used
with matching capacitor for internal
oscillator stabilization.
It is used for external PHY mode with
crystal clock TEST_MODE[3:0]="0001").
* This option is not recommanded with
RTL8201CP.
RTL8201CP - R9 (2K, 1%)
IP101A - R9 (6.2K, 1%)
This schematic sets TEST_MODE to 0001b.
You could set TEST_MODE 0001b or 0010b
in external PHY mode. Refer to datasheet's
detailed description.
CLOCK SOURCE OPTION 1 : 0001b
CLOCK SOURCE OPTION 2 : 0010b
CLOCK SOURCE OPTION 3 : 0001b
< Transformer Specification >
TURN RADIO : TX&RX = 1CT:1CT
INDUCTANCE : 350uH MIN.
* In case of using External PHY mode, use the
transformer which is suitable for external PHY
specification.
Place L1, C23, C24, C25 as close to each power pin as possible.
Place CP1, C26, L2 close to PWFBOUT and place C27 close to PWFBIN.
* RECOMMANDED OPTION
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large enough, the analog and digital grounds can be separated,
which is the ideal configuration. However, if the total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case, all the ground
pins can be connected together to a larger single and intact ground plane.(remove FB3, and change 'GNDA' to 'GND'.)
R9
2K(1%)
Y1
25MHz
RTL8201CP /
IP101A
U2
RTL8201CP / IP101A
MDC
25
MDIO
26
TXD0
6
TXD1
5
TXD2
4
TXD3
3
TXEN
2
TXC
7
RXDV
22
RXD0
21
RXD1
20
RXD2
19
RXD3
18
RXC
16
COL
1
CRS
23
RXER/FXEN
24
X1
46
X2
47
LED0/PHYA0
9
LED1/PHYA1
10
LED2/PHYA2
12
LED3/PHYA3
13
LED4/PHYA4
15
PWFBIN
8
DVDD33
14
DGND
11
DGND
17
PWFBOUT
32
AVDD33
36
DVDD33
48
AGND
29
AGND
35
DGND
45
NC
27
TPRX+
31
TPRX-
30
TPTX-
33
TPTX+
34
RTSET
28
ISOLATE
43
RPTR
40
SPEED
39
DUPLEX
38
ANE
37
LDPS
41
MII/SNIB/RTT3
44
RESETB
42
R4 1.5K
C1
10uF/16V
R7
200
C19
0.1uF
R1
12K(1%)
R11
49.9
C29 18p
C10
0.1uF
L2
100 ohm @ 100Mhz
R15
1M
FB1 1uH
+
C5
10uF/16V
C20
0.1uF
R16
1M
R2
300(1%)
C12
0.1uF
C9
0.1uF
C28 18p
L1
100 ohm @ 100Mhz
R10 5.1K
R12
49.9
Y2
25MHz
R13 5.1K
+
C6
10uF/16V
Y3
25MHz
C21
0.1uF
D1
1SS181(SC-59)
3
1
2
C13
0.1uF
C3
10uF/16V
+
CP1
22uF/16V (Tantal)
R6
49.9
C29 18p
C31 18p
R3
4.7K
C14
0.1uF
C23
0.1uF
R8
200
C2
0.1uF
C28 18p
C28
0.1u
C27
0.1uF
C7
0.1uF
C30 18p
C22
0.1uF
R5
49.9
FB3 1uH
C15
0.1uF
J1
16BIT_EN
1
2
3
C26
0.1uF
FB2
1uH
C17
0.1uF
OSC1
25M (SMD)
x
1
G
2
O
3
V
4
W5300
LQFP100(14X14)
U1
W5300
RSET_BG
1
VCC3A3
2
NC
3
GNDA
4
RXIP
5
RXIN
6
VCC1A8
7
TXOP
8
TXON
9
GNDA
10
VCC1V8
11
GND
12
1V8O
13
VCC3V3
14
GND
15
GNDA
16
VCC1A8
17
BIT16EN
18
TEST_MODE3
19
TEST_MODE2
20
TEST_MODE1
21
TEST_MODE0
22
OP_MODE0
23
OP_MODE1
24
OP_MODE2
25
VCC3V3
26
GND
27
DATA15
28
DATA14
29
DATA13
30
DATA12
31
DATA11
32
DATA10
33
DATA9
34
DATA8
35
VCC1V8
36
GND
37
DATA7
38
DATA6
39
DATA5
40
DATA4
41
DATA3
42
DATA2
43
DATA1
44
DATA0
45
VCC3V3
46
GND
47
ADDR9
48
ADDR8
49
ADDR7
50
ADDR6
51
ADDR5
52
ADDR4
53
ADDR3
54
ADDR2
55
ADDR1
56
ADDR0
57
VCC1V8
58
GND
59
/WR
60
/RD
61
/CS
62
VCC3V3
63
GND
64
/INT
65
/RESET
66
BRDY0
67
BRDY1
68
BRDY2
69
BRDY3
70
MII_RXC
71
VCC1V8
72
GND
73
MII_RXDV
74
MII_RXD0
75
MII_RXD1
76
MII_RXD2
77
MII_RXD3
78
MII_COL
79
/FDX
80
MII_CRS
81
MII_TXC
82
VCC3V3
83
GND
84
/SPDLED(MII_TXD0)
85
/FDXLED(MII_TXD1)
86
/COLLED(MII_TXD2)
87
/RXLED(MII_TXD3)
88
/TXLED(MII_TXEN)
89
/LINKLED
90
OSC25I
91
VCC1V8
92
GND
93
VCC1V8
94
XTLN
95
XTLP
96
GND
97
NC
98
NC
99
NC
100
C16
0.1uF
C25
104
C11
0.1uF
U3
RD1-125BAG1A
TD+
1
TD-
2
TCT
3
NC
4
NC
5
RCT
6
RD+
7
RD-
8
GRN+
10
GRN-
9
YEL+
12
YEL-
11
Shield
13
Shield
14
R14
1M
C24
104
+
C4
3.3uF
C18
0.1uF
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