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MSP430G2553用户指南
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TI公司推出的最新单片机 MSP430G2553 的用户指南,帮助初学者更好的学习。
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MSP430x2xx Family
User's Guide
Literature Number: SLAU144I
December 2004– Revised January 2012
Contents
Preface ...................................................................................................................................... 23
1 Introduction ...................................................................................................................... 25
1.1 Architecture ................................................................................................................. 26
1.2 Flexible Clock System .................................................................................................... 26
1.3 Embedded Emulation ..................................................................................................... 27
1.4 Address Space ............................................................................................................. 27
1.4.1 Flash/ROM ........................................................................................................ 27
1.4.2 RAM ................................................................................................................ 28
1.4.3 Peripheral Modules ............................................................................................... 28
1.4.4 Special Function Registers (SFRs) ............................................................................ 28
1.4.5 Memory Organization ............................................................................................ 28
1.5 MSP430x2xx Family Enhancements .................................................................................... 29
2 System Resets, Interrupts, and Operating Modes .................................................................. 31
2.1 System Reset and Initialization .......................................................................................... 32
2.1.1 Brownout Reset (BOR) .......................................................................................... 32
2.1.2 Device Initial Conditions After System Reset ................................................................. 33
2.2 Interrupts .................................................................................................................... 34
2.2.1 (Non)-Maskable Interrupts (NMI) ............................................................................... 34
2.2.2 Maskable Interrupts .............................................................................................. 37
2.2.3 Interrupt Processing .............................................................................................. 38
2.2.4 Interrupt Vectors .................................................................................................. 40
2.3 Operating Modes .......................................................................................................... 41
2.3.1 Entering and Exiting Low-Power Modes ...................................................................... 43
2.4 Principles for Low-Power Applications .................................................................................. 43
2.5 Connection of Unused Pins .............................................................................................. 44
3 CPU ................................................................................................................................. 45
3.1 CPU Introduction .......................................................................................................... 46
3.2 CPU Registers ............................................................................................................. 47
3.2.1 Program Counter (PC) ........................................................................................... 47
3.2.2 Stack Pointer (SP) ................................................................................................ 48
3.2.3 Status Register (SR) ............................................................................................. 48
3.2.4 Constant Generator Registers CG1 and CG2 ................................................................ 49
3.2.5 General-Purpose Registers R4 to R15 ........................................................................ 50
3.3 Addressing Modes ......................................................................................................... 50
3.3.1 Register Mode .................................................................................................... 52
3.3.2 Indexed Mode ..................................................................................................... 53
3.3.3 Symbolic Mode ................................................................................................... 54
3.3.4 Absolute Mode .................................................................................................... 55
3.3.5 Indirect Register Mode ........................................................................................... 56
3.3.6 Indirect Autoincrement Mode ................................................................................... 57
3.3.7 Immediate Mode .................................................................................................. 58
3.4 Instruction Set .............................................................................................................. 59
3.4.1 Double-Operand (Format I) Instructions ....................................................................... 60
3.4.2 Single-Operand (Format II) Instructions ....................................................................... 61
3.4.3 Jumps .............................................................................................................. 62
3
SLAU144I–December 2004–Revised January 2012 Contents
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Copyright © 2004–2012, Texas Instruments Incorporated
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3.4.4 Instruction Cycles and Lengths ................................................................................. 63
3.4.5 Instruction Set Description ...................................................................................... 65
3.4.6 Instruction Set Details ............................................................................................ 67
4 CPUX .............................................................................................................................. 119
4.1 CPU Introduction ......................................................................................................... 120
4.2 Interrupts .................................................................................................................. 122
4.3 CPU Registers ............................................................................................................ 123
4.3.1 Program Counter (PC) ......................................................................................... 123
4.3.2 Stack Pointer (SP) .............................................................................................. 123
4.3.3 Status Register (SR) ............................................................................................ 125
4.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 126
4.3.5 General-Purpose Registers (R4 to R15) ..................................................................... 127
4.4 Addressing Modes ....................................................................................................... 129
4.4.1 Register Mode ................................................................................................... 130
4.4.2 Indexed Mode ................................................................................................... 131
4.4.3 Symbolic Mode .................................................................................................. 135
4.4.4 Absolute Mode .................................................................................................. 140
4.4.5 Indirect Register Mode ......................................................................................... 142
4.4.6 Indirect Autoincrement Mode .................................................................................. 143
4.4.7 Immediate Mode ................................................................................................ 144
4.5 MSP430 and MSP430X Instructions .................................................................................. 146
4.5.1 MSP430 Instructions ............................................................................................ 146
4.5.2 MSP430X Extended Instructions .............................................................................. 151
4.6 Instruction Set Description .............................................................................................. 164
4.6.1 Extended Instruction Binary Descriptions .................................................................... 165
4.6.2 MSP430 Instructions ............................................................................................ 167
4.6.3 MSP430X Extended Instructions .............................................................................. 219
4.6.4 MSP430X Address Instructions ............................................................................... 261
5 Basic Clock Module+ ........................................................................................................ 277
5.1 Basic Clock Module+ Introduction ..................................................................................... 278
5.2 Basic Clock Module+ Operation ....................................................................................... 280
5.2.1 Basic Clock Module+ Features for Low-Power Applications .............................................. 281
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 281
5.2.3 LFXT1 Oscillator ................................................................................................ 281
5.2.4 XT2 Oscillator ................................................................................................... 282
5.2.5 Digitally-Controlled Oscillator (DCO) ......................................................................... 282
5.2.6 DCO Modulator .................................................................................................. 284
5.2.7 Basic Clock Module+ Fail-Safe Operation ................................................................... 284
5.2.8 Synchronization of Clock Signals ............................................................................. 285
5.3 Basic Clock Module+ Registers ........................................................................................ 287
5.3.1 DCOCTL, DCO Control Register ............................................................................. 288
5.3.2 BCSCTL1, Basic Clock System Control Register 1 ........................................................ 288
5.3.3 BCSCTL2, Basic Clock System Control Register 2 ........................................................ 289
5.3.4 BCSCTL3, Basic Clock System Control Register 3 ........................................................ 290
5.3.5 IE1, Interrupt Enable Register 1 .............................................................................. 291
5.3.6 IFG1, Interrupt Flag Register 1 ................................................................................ 291
6 DMA Controller ................................................................................................................ 293
6.1 DMA Introduction ......................................................................................................... 294
6.2 DMA Operation ........................................................................................................... 296
6.2.1 DMA Addressing Modes ....................................................................................... 296
6.2.2 DMA Transfer Modes ........................................................................................... 297
6.2.3 Initiating DMA Transfers ....................................................................................... 303
4
Contents SLAU144I–December 2004–Revised January 2012
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Copyright © 2004–2012, Texas Instruments Incorporated
www.ti.com
6.2.4 Stopping DMA Transfers ....................................................................................... 304
6.2.5 DMA Channel Priorities ........................................................................................ 305
6.2.6 DMA Transfer Cycle Time ..................................................................................... 305
6.2.7 Using DMA With System Interrupts ........................................................................... 305
6.2.8 DMA Controller Interrupts ...................................................................................... 306
6.2.9 Using the USCI_B I
2
C Module with the DMA Controller ................................................... 306
6.2.10 Using ADC12 with the DMA Controller ...................................................................... 307
6.2.11 Using DAC12 With the DMA Controller ..................................................................... 307
6.2.12 Writing to Flash With the DMA Controller .................................................................. 307
6.3 DMA Registers ........................................................................................................... 308
6.3.1 DMACTL0, DMA Control Register 0 .......................................................................... 309
6.3.2 DMACTL1, DMA Control Register 1 .......................................................................... 309
6.3.3 DMAxCTL, DMA Channel x Control Register ............................................................... 310
6.3.4 DMAxSA, DMA Source Address Register ................................................................... 311
6.3.5 DMAxDA, DMA Destination Address Register .............................................................. 312
6.3.6 DMAxSZ, DMA Size Address Register ....................................................................... 312
6.3.7 DMAIV, DMA Interrupt Vector Register ...................................................................... 313
7 Flash Memory Controller .................................................................................................. 315
7.1 Flash Memory Introduction ............................................................................................. 316
7.2 Flash Memory Segmentation ........................................................................................... 316
7.2.1 SegmentA ........................................................................................................ 317
7.3 Flash Memory Operation ................................................................................................ 318
7.3.1 Flash Memory Timing Generator ............................................................................. 318
7.3.2 Erasing Flash Memory ......................................................................................... 319
7.3.3 Writing Flash Memory .......................................................................................... 322
7.3.4 Flash Memory Access During Write or Erase ............................................................... 327
7.3.5 Stopping a Write or Erase Cycle .............................................................................. 328
7.3.6 Marginal Read Mode ........................................................................................... 328
7.3.7 Configuring and Accessing the Flash Memory Controller ................................................. 328
7.3.8 Flash Memory Controller Interrupts ........................................................................... 328
7.3.9 Programming Flash Memory Devices ........................................................................ 328
7.4 Flash Memory Registers ................................................................................................ 330
7.4.1 FCTL1, Flash Memory Control Register ..................................................................... 331
7.4.2 FCTL2, Flash Memory Control Register ..................................................................... 331
7.4.3 FCTL3, Flash Memory Control Register ..................................................................... 332
7.4.4 FCTL4, Flash Memory Control Register ..................................................................... 333
7.4.5 IE1, Interrupt Enable Register 1 .............................................................................. 333
8 Digital I/O ........................................................................................................................ 335
8.1 Digital I/O Introduction ................................................................................................... 336
8.2 Digital I/O Operation ..................................................................................................... 336
8.2.1 Input Register PxIN ............................................................................................. 336
8.2.2 Output Registers PxOUT ....................................................................................... 336
8.2.3 Direction Registers PxDIR ..................................................................................... 337
8.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ........................................................ 337
8.2.5 Function Select Registers PxSEL and PxSEL2 ............................................................. 337
8.2.6 Pin Oscillator ..................................................................................................... 338
8.2.7 P1 and P2 Interrupts ............................................................................................ 339
8.2.8 Configuring Unused Port Pins ................................................................................. 340
8.3 Digital I/O Registers ..................................................................................................... 341
9 Supply Voltage Supervisor (SVS) ....................................................................................... 343
9.1 Supply Voltage Supervisor (SVS) Introduction ....................................................................... 344
9.2 SVS Operation ........................................................................................................... 345
9.2.1 Configuring the SVS ............................................................................................ 345
5
SLAU144I–December 2004–Revised January 2012 Contents
Submit Documentation Feedback
Copyright © 2004–2012, Texas Instruments Incorporated
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