DM9000AE网络芯片

所需积分/C币:13 2011-09-09 10:59:06 1.84MB PDF
14
收藏 收藏
举报

The DM9000A is a fully integrated and cost-effective processors. The PHY of the DM9000A can interface to the low pin count single chip Fast Ethernet controller with UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with a general processor interface, a 10/100M PHY and AUTO-MDIX. It is fully compliant with the IEEE 802.3u 4K Dword SRAM. It is designed with low power and Spec. Its auto-negotiation function will automatically high performance process that support 3.3V with 5V configure the DM9000A to take the maximum advantage of IO tolerance. its abilities. The DM9000A also supports IEEE 802.3x full-
c (DAVICOM c (DAVICOM c (DAVICOM c (DAVICOM The DM9000A is a fully integrated and cost-effective processors. The PHY of the DM9000A can interface to the low pin count single chip Fast Ethernet controller with UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with a general processor interface, a 10/100M PHY and AUTO-MDIX. It is fully compliant with the lEEE 802.3u 4K Dword SRAM. It is designed with low power and Spec. Its auto-negotiation function will automaticall high performance process that support 3. 3V with 5v configure the DM9000A to take the maximum advantage of lo tolerance its abilities. The DM9000A also supports IEEE 802.3x full duplex fow control The DM9000A supports 8-bit and 16-bit data interfaces to internal memory accesses for various D All Management Autonegotiation Mll Register c (DAVICOM 48-pin LQFP Supports IP/TCP/UDP checksum generation and Supports processor interface: byte/word of I/O checking command to internal memory data operation Supports automatically load vendor Id and Integrated 10/100M transceiver with auto-MDIX product ID from EEPROM Supports back pressure mode for half-duplex Optional EEPROM configuration mode flow control Very low power consumption mode IEEE802. 3x flow control for full-duplex mode Power reduced mode(cable detection Supports wakeup frame, link status change and Power down mode magic packet events for remote wake up Selectable tX drivers for 1: 1 or 1, 25: 1 Integrated 16K Byte SRAM transformers for additional power reduction Build in 3. 3V to 2.5V regulator Compatible with 3. 3V and 5. 0V tolerant 1O Supports early c (DAVICOM ∏ I 萵885帛R8R8 CS# 24sD14 ED2口38 VDD LED1D39 SD15 PWRST# 40 EECS TEST 41 EECK VDD D42 19 H EEDIO 43 SDO 44 SD1 GND 567 16sD2 SD 15 GND RXGND 14 SD3 BGGND 48 SD4 uOm 旨 85品 c (DAVICOM 50nnnnnnnnon 8將高將85R8888 CS#t 37 24 LED3 LED2 23FVDD LED 1 39 WAKE PWRST# 40 EECS TEST口41 20□EECK VDD 42 EEDIO 43 18 X1 44 SD1 GND 45 16SD2 D D46 15 GND RXGND 47 SD3 BGD4● 13[SD4 0 azo× 口 c VVICOM I=Input O= Output 10= Input/Output O/D=Open Drain P= Power # asserted low PD internal pull-low about 60K Pin no Pin name T Description JOR# , PD This pin is low active at default, its polarity can be modified by EEPROM setting See the EEPROM content description for detail Processor Write Command lOW# 1, PD This pin is low active at default, its polarity can be modified by EEPROM setting See the eEProm content description for detail Chip select 37 CS# , PD A default low active signal used to select the DM9000A. Its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Command Type 2 CMD , PD When high, the access of this command cycle is DATA port When low, the access of this command cycle is INDEX port Interrupt Request INT O, PD This pin is high active at default its polarity can be modified by EEPROM setting or by strap pin EECK. See the EEPROM content description for detai 1817,16,1 Processor Data Bus bit 0-7 4,13,12,11 SD0~7 V/O PD 31,29,28,2 Processor data bus bit 8-15 26.25. SD8-15 1/0,PD In 16-bit mode, these pins act as the processor data bus bit 8-15: 22 When EECS pin is pulled high, they have other definitions See 8-bit mode pin description for detail Pin no Pin name Type Description 22/WAKEO, PD ssue a wake up signal when wake up event happens Full-duplex LED In LED mode 1, Its low output indicates that the internal PhY is operated in full-duplex mode, or it is floating for the half-duplex mode of the LED3 O, PD internal PHY In LED mode 0, Its low output indicates that the internal PhY is operated in 10M mode or it is floating for the 100M mode of the internal Phy Note: LED mode is defined in EEPROM setting General Purpose output pins These pins are output only for general purpose that are configured by 25,26,27 GP6~4 O, PD egister 1Fh. GP6 pin also act as trap pin for the INT output type When GP6 is pulled high, the INT is Open-Drain output type Otherwise it is force output type.

...展开详情
试读 57P DM9000AE网络芯片
立即下载 低至0.43元/次 身份认证VIP会员低至7折
一个资源只可评论一次,评论内容不能少于5个字
您会向同学/朋友/同事推荐我们的CSDN下载吗?
谢谢参与!您的真实评价是我们改进的动力~
上传资源赚钱or赚积分
最新推荐
DM9000AE网络芯片 13积分/C币 立即下载
1/57
DM9000AE网络芯片第1页
DM9000AE网络芯片第2页
DM9000AE网络芯片第3页
DM9000AE网络芯片第4页
DM9000AE网络芯片第5页
DM9000AE网络芯片第6页
DM9000AE网络芯片第7页
DM9000AE网络芯片第8页
DM9000AE网络芯片第9页
DM9000AE网络芯片第10页
DM9000AE网络芯片第11页
DM9000AE网络芯片第12页

试读结束, 可继续读6页

13积分/C币 立即下载 >