COM Express™
Carrier Design Guide
Guidelines for designing COM Express™ Carrier Boards
March 13, 2009
Rev. 1.0
This design guide is not a specification. It contains additional detail information but does not replace
the PICMG COM Express™ (COM.0) specification.
For complete guidelines on the design of COM Express™ compliant Carrier Boards and systems,
refer also to the full specification – do not use this design guide as the only reference for any design
decisions. This design guide is to be used in conjunction with COM.0 R1.0.
PICMG COM Express Carrier Board Design Guide Rev. 1.0 / March 13, 2009
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©Copyright 2008, PCI Industrial Computer Manufacturers Group.
The attention of adopters is directed to the possibility that compliance with or adoption of
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®
specifications may require use of an invention covered by patent rights. PICMG
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®
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Prospective users are responsible for protecting themselves against liability for infringement of
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NOTICE:
The information contained in this document is subject to change without notice. The material in
this document details a PICMG
®
specification in accordance with the license and notices set forth
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specification in any company's products.
WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG
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MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR
OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS
FOR PARTICULAR PURPOSE OR USE.
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®
be liable for errors contained herein or for indirect, incidental, special,
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incurred by any user or any third party. Compliance with this specification does not absolve
manufacturers of CompactPCI
®
Express equipment from the requirements of safety and
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PICMG
®
, CompactPCI
®
, AdvancedTCA
®
, ATCA
®
, CompactPCI
®
Express and the PICMG,
CompactPCI, AdvancedTCA and ATCA logos are registered trademarks, and COM Express™,
MicroTCA™, μTCA™, CompactTCA™, AdvancedTCA300™, AdvancedMC™ and SHB
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or product names may be trademarks or registered trademarks of their respective holders.
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Contents
1. Preface..................................................................................................................................8
1.1. About This Document...........................................................................................................8
1.2. Intended Audience................................................................................................................8
1.3. No special word usage.........................................................................................................8
1.4. No statements of compliance..............................................................................................8
1.5. Correctness Disclaimer........................................................................................................8
1.6. Name and logo usage...........................................................................................................9
1.7. Intellectual property............................................................................................................10
1.8. Copyright Notice.................................................................................................................11
1.9. Acronyms and Abbreviations Used...................................................................................12
1.10. Signal Table Terminology...................................................................................................13
2. COM Express Interfaces....................................................................................................15
2.1. COM Express Signals.........................................................................................................15
2.2. PCIe General Introduction..................................................................................................17
2.2.1. COM Express A-B Connector and C-D Connector PCIe Groups....................................17
2.3. General Purpose PCIe Lanes.............................................................................................18
2.3.1. General Purpose PCIe Signal Definitions.......................................................................18
2.3.2. PCI Express Lane Configurations – Per COM Express Spec.........................................19
2.3.3. PCI Express Lane Configurations – Module and Chipset Dependencies.......................19
2.3.4. Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors..................................20
2.3.5. Schematic Examples.......................................................................................................21
2.3.5.1. Reference Clock Buffer..........................................................................................21
2.3.5.2. Reset......................................................................................................................23
2.3.5.3. x1 Slot Example.....................................................................................................23
2.3.5.4. x4 Slot Example.....................................................................................................24
2.3.5.5. PCIe x1 Generic Device Down Example................................................................25
2.3.5.6. PCIe x4 Generic Device Down Example................................................................26
2.3.5.7. PCI Express Mini Card...........................................................................................27
2.3.5.8. ExpressCard...........................................................................................................29
2.3.6. PCI Express Routing Considerations..............................................................................32
2.3.6.1. Polarity Inversion....................................................................................................32
2.3.6.2. Lane Reversal........................................................................................................32
2.4. PEG (PCI Express Graphics)..............................................................................................33
2.4.1. Signal Definitions.............................................................................................................33
2.4.2. PEG Configuration...........................................................................................................34
2.4.2.1. Using PEG Pins for an External Graphics Card......................................................35
2.4.2.2. Using PEG Pins for SDVO.....................................................................................35
2.4.2.3. Using PEG Pins for General Purpose PCIe Lanes.................................................35
2.4.3. Reference Schematics.....................................................................................................37
2.4.3.1. x1, x4, x8, x16 Slot.................................................................................................37
2.4.4. Routing Considerations...................................................................................................38
2.4.4.1. Polarity Inversion....................................................................................................38
2.4.4.2. Lane Reversal........................................................................................................38
2.5. SDVO....................................................................................................................................40
2.5.1. Signal Definitions.............................................................................................................40
2.5.1.1. SDVO Port Configuration........................................................................................40
2.5.1.2. Supported SDVO Devices......................................................................................41
2.5.2. Reference Schematics.....................................................................................................42
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2.5.2.1. SDVO to DVI Transmitter Example........................................................................42
2.5.2.2. Other SDVO Output Options: LVDS, NTSC............................................................43
2.5.3. Routing Considerations...................................................................................................44
2.5.3.1. SDVO Option – PEG Lane Reversal......................................................................44
2.6. LAN.......................................................................................................................................45
2.6.1. Signal Definitions.............................................................................................................45
2.6.1.1. Status LED Signal Definitions.................................................................................45
2.6.1.2. LAN 1 and 2 shared with IDE.................................................................................46
2.6.1.3. PHY / Magnetics Connections................................................................................46
2.6.2. Reference Schematics.....................................................................................................48
2.6.2.1. Magnetics Integrated Into RJ-45 Receptacle..........................................................48
2.6.2.2. Discrete Coupling Transformer...............................................................................49
2.6.3. Routing Considerations...................................................................................................50
2.6.3.1. Reference Ground Isolation and Coupling..............................................................50
2.7. USB Ports............................................................................................................................51
2.7.1. Signal Definitions.............................................................................................................51
2.7.1.1. USB Over-Current Protection (USB_x_y_OC#)......................................................51
2.7.1.2. Powering USB devices during S5...........................................................................51
2.7.1.3. USB connector.......................................................................................................52
2.7.2. Reference Schematics.....................................................................................................52
2.7.3. Routing Considerations...................................................................................................55
2.7.3.1. EMI / ESD Protection .............................................................................................55
2.8. SATA.....................................................................................................................................56
2.8.1. Signal Definitions.............................................................................................................56
2.8.2. Reference Schematic......................................................................................................58
2.8.3. Routing Considerations...................................................................................................59
2.9. LVDS.....................................................................................................................................60
2.9.1. Signal Definitions.............................................................................................................60
2.9.1.1. Connector and Cable Considerations.....................................................................61
2.9.1.2. Display Timing Configuration..................................................................................61
2.9.1.3. Backlight Control....................................................................................................61
2.9.1.4. Color Mapping and Terms......................................................................................62
2.9.1.5. Note on Industry Terms..........................................................................................63
2.9.1.6. LVDS Display Color Mapping Tables......................................................................64
2.9.2. Reference Schematics.....................................................................................................66
2.9.3. Routing Considerations...................................................................................................67
2.10. IDE and CompactFlash (PATA)...........................................................................................68
2.10.1. Signal Definitions.............................................................................................................68
2.10.2. IDE 40-Pin Header (3.5 Inch Drives)...............................................................................69
2.10.3. IDE 44-Pin Header (2.5 Inch and Low Profile Optical Drives).........................................69
2.10.4. CompactFlash 50 Pin Header.........................................................................................69
2.10.5. IDE / CompactFlash Reference Schematics...................................................................69
2.10.6. Routing Considerations...................................................................................................70
2.11. VGA......................................................................................................................................71
2.11.1. Signal Definitions.............................................................................................................71
2.11.2. VGA Connector................................................................................................................71
2.11.3. VGA Reference Schematics............................................................................................72
2.11.4. Routing Considerations...................................................................................................73
2.11.4.1. RGB Analog Signals...............................................................................................73
2.11.4.2. HSYNC and VSYNC Signals..................................................................................73
2.11.4.3. DDC Interface.........................................................................................................73
2.11.4.4. ESD Protection/EMI................................................................................................73
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2.12. TV-Out..................................................................................................................................74
2.12.1. Signal Definitions.............................................................................................................74
2.12.2. TV-Out Connector............................................................................................................74
2.12.3. TV-Out Reference Schematics........................................................................................76
2.12.4. Routing Considerations...................................................................................................77
2.12.4.1. Signal Termination..................................................................................................77
2.12.4.2. Video Filter.............................................................................................................77
2.12.4.3. ESD Protection.......................................................................................................77
2.13. AC'97 and HDA Digital Audio Interfaces............................................................................78
2.13.1. Signal Definitions.............................................................................................................78
2.13.2. Reference Schematics.....................................................................................................80
2.13.2.1. AC'97......................................................................................................................80
2.13.2.2. High Definition Audio (HDA)...................................................................................82
2.13.3. Routing Considerations...................................................................................................83
2.14. PCI Bus................................................................................................................................84
2.14.1. Signal Definitions.............................................................................................................84
2.14.2. Reference Schematics.....................................................................................................85
2.14.2.1. Resource Allocation................................................................................................85
2.14.2.2. Device-Down Example...........................................................................................87
2.14.2.3. Device-Down Considerations.................................................................................88
2.14.2.4. Clock Buffer............................................................................................................88
2.14.3. Routing Considerations...................................................................................................88
2.14.3.1. General PCI Signals...............................................................................................88
2.14.3.2. PCI Clock Routing..................................................................................................88
2.15. LPC Bus – Low Pin Count Interface..................................................................................90
2.15.1. Signal Definition...............................................................................................................90
2.15.2. LPC Bus Reference Schematics.....................................................................................90
2.15.2.1. LPC Bus Clock Signal............................................................................................90
2.15.2.2. LPC Reset Signal...................................................................................................91
2.15.2.3. LPC Firmware Hub.................................................................................................92
2.15.2.4. LPC PLD Example – Port 80 Decoder....................................................................94
2.15.2.5. SuperIO..................................................................................................................95
2.15.3. Routing Considerations...................................................................................................96
2.15.3.1. General Signals......................................................................................................96
2.15.3.2. Bus Clock Routing..................................................................................................96
2.16. General Purpose I2C Bus Interface...................................................................................98
2.16.1. Signal Definitions.............................................................................................................98
2.16.2. Reference Schematics.....................................................................................................98
2.16.3. Routing Considerations...................................................................................................99
2.17. System Management Bus (SMBus).................................................................................100
2.17.1. Signal Definitions...........................................................................................................100
2.17.2. Reference Schematics..................................................................................................101
2.17.3. Routing Considerations.................................................................................................101
2.18. Miscellaneous Signals......................................................................................................102
2.18.1. Module Type Detection..................................................................................................102
2.18.2. Speaker Output..............................................................................................................103
2.18.3. RTC Battery Implementation.........................................................................................104
2.18.3.1. RTC Battery Lifetime............................................................................................104
2.18.4. Power Management Signals..........................................................................................105
2.18.5. Watchdog Timer.............................................................................................................107
2.18.6. General Purpose Input/Output (GPIO)..........................................................................108
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