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PCI-to-PCI Bridge Architecture Specification
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PCI-to-PCI Bridge Architecture Specification,作为 PCI local bus的扩展,主要描述了对pci桥的建议。不知道怎么搞的把下载所需积分改小后,系统会自动把积分改回来,如果觉得积分太多就联系我吧
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PCI-to-PCI Bridge
Architecture Specification
Revision 1.2
June 9, 2003
PCI-TO-PCI BRIDGE ARCHITECTURE SPECIFICATION, REV 1.2
2
Revision History
REVISION ISSUE DATE COMMENTS
1.0 04/05/94 Original issue.
1.1 12/18/98 Updated to include target initial latency requirements.
1.2 06/09/03
Incorporated the VGA 16-bit ECR, the SSID/SSVID ECR, added
interrupt disable and status bits, and updated add-in card and
system board terminology.
PCI-SIG disclaims all warranties and liability for the use of this document and the
information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding the PCI-to-PCI Bridge Architecture Specification or membership in
PCI-SIG may be forwarded to:
Membership Services
http://www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-291-2569
Fax: 503-297-1090
Technical Support
Technical Support for this specification is available to members. For information,
please visit: http://www.pcisig.com/developers/technical_support.
DISCLAIMER
This PCI-to-PCI Bridge Architecture Specification is provided “as is” with no
warranties whatsoever, including any warranty of merchantability, noninfringement,
fitness for any particular purpose, or any warranty otherwise arising out of any
proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of
proprietary rights, relating to use of information in this specification. No license,
express or implied, by estoppel or otherwise, to any intellectual property rights is
granted herein.
PCI-SIG is a trademark of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their
respective owners.
Copyright © 1994, 1998, 2003, PCI-SIG
PCI-TO-PCI BRIDGE ARCHITECTURE SPECIFICATION, REV 1.2
3
Contents
PREFACE ......................................................................................................................... 11
1. INTRODUCTION .................................................................................................... 13
1.1. GOALS AND NON-GOALS OF THIS SPECIFICATION ............................................. 13
1.2. O
VERVIEW AND
T
ERMINOLOGY
......................................................................... 13
2. BRIDGE REQUIREMENTS.................................................................................... 17
2.1. S
UMMARY OF
K
EY
R
EQUIREMENTS
................................................................... 17
2.2. CAPABILITIES NOT SUPPORTED ......................................................................... 18
2.3. OPTIONAL CAPABILITIES ................................................................................... 19
3. CONFIGURATION.................................................................................................. 21
3.1. O
VERVIEW OF
H
IERARCHICAL
C
ONFIGURATION
................................................ 21
3.1.1. Type 0 Configuration Transaction Support .............................................. 22
3.1.2. Type 1 Configuration Transaction Support .............................................. 22
3.1.2.1. Primary Interface .............................................................................. 22
3.1.2.1.1. Type 1 to Type 0 Conversion......................................................... 23
3.1.2.1.2. Type 1 to Type 1 Forwarding ........................................................ 24
3.1.2.1.3. Type 1 to Special Cycle Conversion.............................................. 25
3.1.2.2. Secondary Interface .......................................................................... 25
3.1.2.2.1. Type 1 to Type 1 Forwarding ........................................................ 26
3.1.2.2.2. Type 1 to Special Cycle Conversion.............................................. 26
3.2. PCI-TO-PCI BRIDGE CONFIGURATION SPACE HEADER FORMAT....................... 27
3.2.1. Accessing Reserved Registers................................................................... 28
3.2.2. Accessing Reserved Bit Fields .................................................................. 28
3.2.3. Reset Events .............................................................................................. 28
3.2.4. Common Format Configuration Registers................................................ 28
3.2.4.1. Vendor ID Register........................................................................... 28
3.2.4.2. Device ID Register............................................................................ 28
3.2.4.3. Command Register............................................................................ 29
3.2.4.4. Status Register .................................................................................. 32
3.2.4.5. Revision ID Register......................................................................... 36
3.2.4.6. Class Code Register .......................................................................... 36
3.2.4.7. Cacheline Size Register .................................................................... 37
3.2.4.8. Latency Timer Register..................................................................... 37
3.2.4.9. Header Type Register ....................................................................... 37
3.2.4.10. BIST Register.................................................................................... 37
PCI-TO-PCI BRIDGE ARCHITECTURE SPECIFICATION, REV 1.2
4
3.2.5. Bridge Specific Configuration Registers .................................................. 38
3.2.5.1. Base Address Registers..................................................................... 38
3.2.5.1.1. Memory Base Address Register Format ........................................ 39
3.2.5.1.2. I/O Base Address Register Format ................................................ 40
3.2.5.2. Primary Bus Number Register.......................................................... 41
3.2.5.3. Secondary Bus Number Register...................................................... 41
3.2.5.4. Subordinate Bus Number Register.................................................... 41
3.2.5.5. Secondary Latency Timer Register................................................... 41
3.2.5.6. I/O Base Register and I/O Limit Register......................................... 42
3.2.5.7. Secondary Status Register................................................................. 43
3.2.5.8. Memory Base Register and Memory Limit Register........................ 46
3.2.5.9. Prefetchable Memory Base Register and Prefetchable Memory Limit
Register ........................................................................................................... 46
3.2.5.10. Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32
Bits Registers ........................................................................................................ 47
3.2.5.11. I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits Registers....... 48
3.2.5.12. Capabilities Pointer........................................................................... 48
3.2.5.13. Subsystem ID and Subsystem Vendor ID......................................... 48
3.2.5.14. Reserved Registers at 35h, 36h, and 37h .......................................... 49
3.2.5.15. Expansion ROM Base Address Register .......................................... 49
3.2.5.16. Interrupt Line Register...................................................................... 50
3.2.5.17. Interrupt Pin Register........................................................................ 50
3.2.5.18. Bridge Control Register .................................................................... 50
3.2.6. Slot Numbering Capabilities List Item...................................................... 56
3.2.6.1. Slot Numbering Capabilities ID........................................................ 56
3.2.6.2. Pointer to Next ID............................................................................. 56
3.2.6.3. Add-in Card Slot Register................................................................. 56
3.2.6.4. Chassis Number Register.................................................................. 57
4. ADDRESS DECODING .......................................................................................... 59
4.1. ADDRESS RANGES ............................................................................................. 59
4.2. I/O ..................................................................................................................... 59
4.2.1. ISA Mode................................................................................................... 61
4.3. MEMORY MAPPED I/O ....................................................................................... 62
4.4. PREFETCHABLE MEMORY .................................................................................. 63
4.4.1. 64-bit Addressing...................................................................................... 64
4.4.2. 64-bit Address Decoding of Prefetchable Memory................................... 66
4.4.2.1. Below the 4-GB Boundary................................................................ 67
4.4.2.2. Above the 4-GB Boundary ............................................................... 67
4.4.2.3. Across the 4-GB Boundary............................................................... 67
4.5. VGA SUPPORT .................................................................................................. 68
4.5.1. VGA Compatible Addressing .................................................................... 68
4.5.2. VGA Palette Snooping .............................................................................. 69
4.6. SUBTRACTIVE DECODE SUPPORT ....................................................................... 69
PCI-TO-PCI BRIDGE ARCHITECTURE SPECIFICATION, REV 1.2
5
5. BUFFER MANAGEMENT ..................................................................................... 71
5.1. PREFETCHING READ DATA ................................................................................ 71
5.2. P
OSTING
W
RITE
D
ATA
....................................................................................... 72
5.2.1. Memory Write and Invalidate Usage........................................................ 73
5.2.1.1. Forwarding Memory Write and Invalidate Transactions.................. 73
5.2.1.2. Promoting Memory Write Transactions ........................................... 74
5.2.1.3. Combining Memory Write Transactions .......................................... 74
5.2.1.4. Memory Write and Invalidate Disconnects ...................................... 75
5.2.1.4.1. Master Disconnected by the Bridge............................................... 75
5.2.1.4.2. Bridge Disconnected by the Target................................................ 75
5.3. D
ELAYED
T
RANSACTIONS
.................................................................................. 75
5.3.1. Discarding a Delayed Request.................................................................. 77
5.3.2. Discarding a Delayed Completion............................................................ 77
5.4. E
XCLUSIVE
A
CCESS
T
RANSACTIONS
.................................................................. 78
5.4.1. Delayed Lock-Request Error .................................................................... 78
5.4.2. Normal Completion................................................................................... 79
5.5. O
RDERING
R
EQUIREMENTS
................................................................................ 80
5.5.1. Summary of PCI Ordering Requirements................................................. 80
5.5.1.1. General Requirements....................................................................... 80
5.5.1.2. Delayed Transaction Requirements .................................................. 81
5.5.2. Ordering of Requests ................................................................................ 81
5.5.3. Ordering of Delayed Transactions ........................................................... 83
5.5.4. Transactions That Have No Ordering Constraints................................... 86
5.5.5. Delayed Transactions and LOCK#........................................................... 87
5.5.6. Error Conditions....................................................................................... 88
5.5.7. Illustrations of the Use of the Ordering Rules.......................................... 88
5.6. SPECIAL DESIGN CONSIDERATIONS ................................................................... 92
5.6.1. Read Starvation......................................................................................... 92
5.6.2. Stale Data.................................................................................................. 93
5.6.3. Deadlocks.................................................................................................. 94
5.7. C
OMBINING
S
EPARATE
W
RITES
I
NTO A
S
INGLE
B
URST
T
RANSACTION
.............. 95
5.8. MERGING SEPARATE WRITES INTO A SINGLE TRANSACTION............................. 96
5.9. COLLAPSING OF WRITES .................................................................................... 96
6. ERROR SUPPORT................................................................................................... 97
6.1. INTRODUCTION .................................................................................................. 97
6.2. PARITY ERRORS ................................................................................................. 99
6.2.1. Address Parity Errors............................................................................... 99
6.2.2. Read Data Parity Errors......................................................................... 100
6.2.2.1. Target Completion Error................................................................. 100
6.2.2.2. Master Completion Error ................................................................ 101
6.2.3. Non-Posted Write Data Parity Errors .................................................... 102
6.2.3.1. Master Request Error ...................................................................... 102
6.2.3.2. Target Completion Error................................................................. 103
6.2.3.3. Master Completion Error ................................................................ 103
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