SiI 9125/9135 HDMI Receiver
Programmer's Reference
Silicon Image, Inc.
Video Status Register............................................................................................................................ 22
Video Horizontal Front Porch Registers................................................................................................ 22
Video HSYNC Active Width Register .................................................................................................... 23
Video Pixel Clock Timing Registers ...................................................................................................... 24
Video Processing Registers .................................................................................................................. 25
Video Mode #1 Register........................................................................................................................ 25
Video Mode #2 Register........................................................................................................................ 26
Video Digital Blank Value Register........................................................................................................ 27
Video Control Register .......................................................................................................................... 28
Video Field2 Back Porch Mode Register .............................................................................................. 28
Video Channel Mapper Register ........................................................................................................... 29
Video Control #2 Register ..................................................................................................................... 29
Deep Color Status Register................................................................................................................... 29
Auto Video Control Registers................................................................................................................ 30
Auto Output Format Register ................................................................................................................ 30
Interrupt Registers.................................................................................................................................. 31
Interrupt State Register ......................................................................................................................... 31
Interrupt Unmask Registers .................................................................................................................. 31
Interrupt Control Register ...................................................................................................................... 31
Interrupt Status #1 Register................................................................................................................... 33
Interrupt Status #2 Register................................................................................................................... 34
Interrupt Status #3 Register................................................................................................................... 35
Interrupt Status #4 Register................................................................................................................... 36
Interrupt Packet Control Register.......................................................................................................... 37
Interrupt Status #5 Register................................................................................................................... 38
Interrupt Status #6 Register................................................................................................................... 39
Interrupt Status #7 Register................................................................................................................... 39
TMDS Analog Core Registers................................................................................................................ 40
TMDS Analog Control #2 Register ........................................................................................................ 40
TMDS Termination Control Register ..................................................................................................... 41
Auto Audio and Video Control............................................................................................................... 42
Auto Control Register ............................................................................................................................ 42
ECC Control Registers ........................................................................................................................... 43
ECC Control Register............................................................................................................................ 43
BCH Threshold Register ....................................................................................................................... 43
ECC T4 Corrected Threshold Register ................................................................................................. 43
ECC T4 Uncorrected Threshold Register ............................................................................................. 43
ECC Error Threshold and Count Registers........................................................................................... 44
AEC Exception Enable Registers.......................................................................................................... 45
AEC Video Configuration Mask Registers ............................................................................................ 47
HDCP Repeater Registers...................................................................................................................... 48
Downstream BSTATUS Registers (SiI 9135 Only)................................................................................ 48
Downstream M0 Registers (SiI 9135 Only)........................................................................................... 48
Downstream VH Register (SiI 9135 Only)............................................................................................. 49
Sink-Accessible Registers at Device Address 0x68 ............................................................................... 50
Audio Clock Recovery (ACR) Registers............................................................................................... 50
ACR Control Register #1....................................................................................................................... 50
ACR Audio Frequency Register ............................................................................................................ 51
ACR N Value Registers ......................................................................................................................... 51
ACR CTS Value Registers .................................................................................................................... 52
ACR PLL Lock Value Registers............................................................................................................. 53
R Hardware Extracted Fs Register ....................................................................................................... 54
ACR Control #3 Register....................................................................................................................... 54
ACR Configuration Registers ................................................................................................................ 55
SiI-PR-0042-A03 iv © 2007 Silicon Image, Inc. CONFIDENTIAL
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2017-12-01
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时空引力511510452018-04-249135是最经典的HDMI采集方案了
FireBirdCN2019-01-10下载用来做9287
