A3967的英文数据手册。 The A3967 is a complete microstepping motor driver with builtin translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 30 V and ±750 mA. The A3967 includes a fixed off-time current regulator that ha
Load Supply voltage Range NBB Operating 4.75 30 During sleep mode 0 30 V Output Leakage current CEX OUT BB <1.0 20 UA VOuT=0v U 开T -1.0 20 A Output Saturation Voltage VCE(sat) Source driver, IOUT=-750 mA 19 2.1 V Source driver, IOuT =-400 mA 2.0 Sink driver, IouT =750 mA 0.65 1.3 Sink driver, IOuT =400 mA 0.21 0.5 Clamp Diode Forward Voltage VE IF=750 mA 1.4 1.6 400mA 1.4 Motor Supply Current Outputs enabled 5.0 A RESET high 200 HA Sleep mode UA Logic Supply Voltage Range Vcc Operating Logic Input Voltage V 0.vCc V 0.3V Logic Input Current N(1) VIN=0.7V CC 20 <1.0 20 卩A 10 VIN=0. 3Vcc 20 <1.0 20 A Maximum STEP Frequency ISTEP 500* kHz Blank time tBLANK R=56K0,C=680pF7009501200 ns Fixed Off Time tR=56k0,c1=680pF30 38 46 us continued next page Full step(2 phase) L Half H Quarter step Eighth step Allegro Allegro MicroSystems. LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com Mixed Decay Trip Point PF FDH 0.vCc PFDL 0.21Vc CC Ref Input Voltage Range V REF Operating 1.0 Vcc V Reference Input Impedance REF 120 160 200 kQ Gain(Gm)Error E VREF =2 V, Phase Current=38. 37%t ±10 (note 3) VREF =2 V, Phase Current =7071% t ±50 VREF =2 V, Phase Current =100.00%t ±5.0 Thermal Shutdown Temp 165 Thermal Shutdown Hysteresis △TJ 15 UVLO Enable threshold UVLO Increasing VcC 2.45 2.7 2.95 V UVLO Hysteresis △ VUVLO 0.05 0.10 Logic Supply Currer cc Outputs enabled 50 m A Outputs off 90 MA Sleep mode LA Operation at a step frequency greater than the specified minimum value is possible but not warranteed t 8 microstep/step operation NOTES: 1. Typical Data is for design information only 2. Negative current is defined as coming out of (sourcing)the specified device terminal 3. EG=(IVREF/8]-VSENSE(VREF/8) Allegro Allegro MicroSystems. LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com The A3967 is a complete microstep Input terminals ping motor driver with built in translator for easy operation MSI and MS, sclect the microstepping format per with minimal control lines. It is designed to operate bipolar table 1. Changes to these inputs do not take effect until the stepper motors in full-, half-, quarter-and eighth-step STEP command(see figure modes. The current in each of the two output full bridges is regulated with fixed off time pulse-width modulated The state of the direction (PWM) control circuitry. The full-bridge current at each input will determine the direction of rotation of the motor step is set by the value of an external current sense resis Each full bridge is tor(rs), a reference voltage (VREF), and the DACs output controlled by a fixed off-time PWM current-control cir- voltage controlled by the output of the translator cuit that limits the load current to a desired value (IRip) At power up, or reset, the translator sets the DACs and Initially, a diagonal pair of source and sink outputs are phase current polarity to initial home state(see figures for enabled and current flows through the motor winding and home-state conditions), and sets the current regulator for Rs. When the voltage across the current-sense resistor both phases to mixed-decay mode When a step command equals the dac output voltage, the current-sense compara gnal occurs on the StEp input the translator automati tor resets the pwm latch which turns off the source driver cally sequences the daCs to the next level(sce table 2 for (slow-decay mode)or the sink and source drivers(fast-or the current level sequence and current polarity) The mic- mixed-decay modes) roster resolution is set by inputs MS and Ms, as shown in The maximum value of current limiting is set by the tablc I If the new DAC output levcl is lower than the prc- selection of Rs and the voltage at the VreF input with a vious level the decay mode for that full bridge will be set transconductance function approximated by by the PFD input(fast, slow or mixed decay ) If the new DAC level is higher or equal to the previous level then the TRIPmax VREr/8Rs decay mode for that Full bridge will be slow decay. This The daC output reduces the VReF output to the cur- automatic current-decay selection will improve microstep rent-sense comparator in precise steps(see table 2 for ping performance by reducing the distortion of the current ITRIPmax at each step) waveform due to the motor beMF TRIP =(%ITRIPmax/100) X ITRIPmax The reset input(active low sets the translator to a predefined home state(see figures The internal pwm current-control for home state conditions) and turns off all of the outputs circuitry uses a one shot to control the time the driver(s STEP inputs are ignored until the RESet input goes high. remain(s)off. The one shot off-time, toff, is determined by the selection of an external resistor(rT)and capacitor(C A low-to-high transition on the connected from the rC timing terminal to ground. The off STEP input sequences the translator and advances the time, over a range of values of ct=470 pF to 1500 pF and motor one increment. The translator controls the input to RT=12 kn2 to 100 kS2 is approximated by the dacs and the direction of current fow in each wind ing The size of the increment is determined by the state of RC inputs MS and Ms(see table 1) Allegro legro Micro Systems LLC 115Ne 1508.853.5000:www.allearomicro.com In addition to the fixed off-time of the When a STEP input PWM control circuit, the Cr component sets the compara signal commands a lower output current from the previous tor blanking time. This function blanks the output of the step, it switches the output current decay to either slow current-sense comparator when the outputs are switched by fast-, or mixcd-decay depending on the voltage levcl at the the internal current-control circuitry. The comparator out PFD input. If the voltage at the pfd input is greater than put is blanked to prevent false overcurrent detection due 0.6Vcc then slow-decay mode is selected. If the voltage on to reverse recovery currents of the clamp diodes, and/or the pfd input is less than 0.21Vcc then fast-decay mode is switching transients related to the capacitance of the load. selected Mixed decay is between these two levels The blank time tBLANK can be approximated by If the voltage on the PFD in BLANK 1400C T put is between 0.6Vcc and 0.21VcC, the bridge will oper ate in mixed-decay mode depending on the step sequence This active-low input enables (scc figures). As the trip point is reached, the device will all of the outputs. When logic high the outputs are dis go into fast-decay mode until the voltage on the rc termi abled. Inputs to the translator(STEP, DIRECTION, MS1 nal decays to the voltage applied to the Pfd terminal. The MS)are all active independent of the enable input time that the device operates in fast decay is approximated state b In the event of a fault(excessive junction tED=RTCTIn(0.vCc/Vpep temperature)the outputs of the device are disabled until the fault condition is removed. At power up, and in the After this fast decay portion, tED, the device will event of low Vcc, the under-voltage lockout(UVLO) switch to slow-decay mode for the remainder of the fixed circuit disables the drivers and resets the translator to the off-time period home state An active-low control input used to minimize power consumption when not in use. This dis ables much of the internal circuitry including the outputs TA=+25°C A logic high allows normal operation and startup of the device in the home position ∽=>zug 2.0 SOURCE DRIVER 1.0 zo=5=∽H2 0.5 SINK DRIVER 200 300 400 500 600 700 OUTPUT CURRENT IN MILLIAMPERES Dwg. GP 064-1A Allegro MicroSystems. LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com (TA=+25C, Vcc =5 V, Logic Levels are Vcc and Ground STEP 50% D MS1/MS2 DIR/RESET E Dwg. WP-042 A. Minimum command active time Before Step Pulse(Data Set-Up Time)..... 200 ns B. Minimum Command Active Time After Step Pulse(Data Hold Time) 200ns C. Minimum StEP Pulse width 1.0μs D. Minimum step low time 0μs E. Maximum Wake-Up Time 1.0ms Allegro legro Micro Systems LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com The printed wiring board should use a heavy To minimize inaccuracies caused by ground plane ground-trace ir drops in sensing the For optimum electrical and thermal performance, the the current-sense resistor (Rs)should have an indepen- dent ground return to the star ground of the device. This driver should be soldered directly onto the board path should be as short as possible. For low-value sense The load supply terminal, VBB, should be decoupled resistors the ir drops in the printed wiring board scnsc with an electrolytic capacitor (>47 uF is recommended resistor's traces can be significant and should be taken into placed as close to the device as possible account. The use of sockets should be avoided as they can introduce variation in Rs due to their contact resistance To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output Allegro micro Systems recommends a value ofrs traces away from the sensitive logic-input traces. Always given by drive the logic inputs with a low source impedance to Rs=0.5/TRIpmax Increase noise immunity Circuitry turns off all drivers when A star ground system located close to the the junction temperature reaches 165C, typically It is driver is recommended intended only to protect the device from failures due to The 24-lead soiC has the analog ground and the excessive junction temperatures and should not imply power ground internally bonded to the power tabs of the output short circuits are permitted. Thermal shutdown has package(leads 6, 7, 18, and 19) a hysteresis of approximately 15C Allegro MicroSystems. LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com Table 2 Step Sequencing Home State 45 Step angle, DIR= H Phase 1 Current Phase 2 Current Full Step Half Step 14Step 18 Step trimax) (%L Step Angle ripa (%) 100.00 0.00 0.0 2 9808 19.51 113 92.39 3827 22.5 4 83.15 5556 33.8 70.71 70.71 45.0 6 5556 83.15 563 38.27 92.39 67.5 8 19.51 98.08 78.8 5 0.00 10000 90.0 10 19.51 98.08 101.3 11 38.27 92.39 112.5 12 55.56 83.15 123.8 7 13 70.71 70.71 135.0 14 83.15 55.56 146.3 8 15 2.39 38.27 157.5 6 98.08 19.51 168.8 17 100.00 0.00 180.0 98.08 -19.51 191.3 19 92.39 38.27 202.5 20 83.15 -55.56 213.8 6 21 70.71 70.71 225.0 55.56 83.15 236.3 38.27 92.39 247.5 19.51 98.08 258.8 13 0.00 10000 270.0 19.51 98.08 281.3 14 27 38.27 92.39 292.5 28 5556 83.15 303.8 15 70.71 -70.71 315.0 83.15 -55.56 326.3 31 92.39 38.27 337.5 98.08 -19.51 348.8 legro Micro Systems LLC 115Ne Worcester, Massachusetts 01615-0036 U.S.A 1508.853.5000:www.allearomicro.com MS,=MS2=L, DIR=H The vector addition of the output currents at any step is 100% Allegro legro Micro Systems LLC 115Ne 1508.853.5000:www.allearomicro.com