没有合适的资源?快使用搜索试试~ 我知道了~
OMAP3530数据手册
4星 · 超过85%的资源 需积分: 9 7 下载量 40 浏览量
2011-12-12
11:31:13
上传
评论
收藏 21.83MB PDF 举报
温馨提示
试读
3549页
omap3530数据使用手册OMAP3530\OMAP35X Technical Reference Manual.pdf
资源详情
资源评论
资源推荐
OMAP35x Applications Processor
Texas Instruments OMAP™ Family of Products
Technical Reference Manual
Literature Number: SPRUF98D
October 2009
Contents
1 Introduction .................................................................................................................... 153
1.1 Overview .................................................................................................................. 154
1.1.1 OneDRAM Implementation .................................................................................... 155
1.2 Environment .............................................................................................................. 156
1.3 Description ................................................................................................................ 157
1.3.1 MPU Subsystem ................................................................................................ 158
1.3.2 IVA2.2 Subsystem .............................................................................................. 158
1.3.3 On-Chip Memory ................................................................................................ 159
1.3.4 External Memory Interfaces ................................................................................... 159
1.3.5 DMA Controllers ................................................................................................. 160
1.3.6 Multimedia Accelerators ........................................................................................ 160
1.3.7 Security (HS Devices Only) .................................................................................... 161
1.3.8 Comprehensive Power Management ......................................................................... 161
1.3.9 Peripherals ....................................................................................................... 161
1.4 Package-On-Package Concept ........................................................................................ 163
1.5 OMAP35x Family ........................................................................................................ 165
1.5.1 Device Features ................................................................................................. 165
1.5.2 Device Identification ............................................................................................ 167
1.5.2.1 720MHz Device Identification ........................................................................... 171
1.5.2.1.1 Procedure for Calculation of SmartReflex nValue for OPP6 ................................... 171
1.5.3 General Recommendations Relative to Unavailable Features/Modules ................................. 171
1.6 Revision History .......................................................................................................... 173
2 Memory Mapping ............................................................................................................. 175
2.1 Introduction ............................................................................................................... 176
2.2 Global Memory Space Mapping ....................................................................................... 178
2.3 L3 and L4 Memory Space Mapping ................................................................................... 181
2.3.1 L3 Memory Space Mapping ................................................................................... 181
2.3.2 L4 Memory Space Mapping ................................................................................... 182
2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 182
2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 185
2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 186
2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 187
2.3.3 Register Access Restrictions .................................................................................. 188
2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 189
2.4.1 IVA2.2 Subsystem Internal Memories and Cache Allocation ............................................. 190
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 190
2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 191
2.4.2 DSP Access to L2 Memories .................................................................................. 192
2.4.2.1 DSP Access to L2 ROM ................................................................................. 192
2.4.2.2 DSP Access to L2 RAM ................................................................................. 192
2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 192
2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 193
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 193
2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... 195
2.5 Revision History .......................................................................................................... 196
3
SPRUF98D–October 2009 Contents
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
www.ti.com
3 MPU Subsystem .............................................................................................................. 197
3.1 MPU Subsystem Overview ............................................................................................. 198
3.1.1 Introduction ...................................................................................................... 198
3.1.2 Features .......................................................................................................... 199
3.2 MPU Subsystem Integration ............................................................................................ 200
3.2.1 MPU Subsystem Clock and Reset Distribution ............................................................. 202
3.2.1.1 Clock Distribution ......................................................................................... 202
3.2.1.2 Reset Distribution ......................................................................................... 203
3.2.2 ARM Subchip .................................................................................................... 204
3.2.2.1 ARM Overview ............................................................................................ 204
3.2.2.2 ARM Description .......................................................................................... 205
3.2.2.2.1 ARM
®
Cortex™-A8 Instruction, Data, and Private Peripheral Port ........................... 205
3.2.2.2.2 MPU Subsystem Features .......................................................................... 205
3.2.2.3 Clock, Reset, and Power Management ................................................................ 206
3.2.2.3.1 Clocks .................................................................................................. 206
3.2.2.3.2 Reset ................................................................................................... 206
3.2.2.3.3 Power Management ................................................................................. 206
3.2.3 AXI2OCP and I2Async Bridges ............................................................................... 206
3.2.3.1 Bridges Overview ......................................................................................... 206
3.2.3.2 AXI2OCP Description .................................................................................... 207
3.2.3.3 AXI Tag to OCP Thread Remapping ................................................................... 208
3.2.3.4 Clocks, Reset, and Power Management .............................................................. 208
3.2.3.4.1 Clocks .................................................................................................. 208
3.2.3.4.2 Reset ................................................................................................... 209
3.2.3.4.3 Power Management ................................................................................. 209
3.2.4 Interrupt Controller .............................................................................................. 209
3.2.4.1 Clocks ...................................................................................................... 209
3.2.4.2 Reset ....................................................................................................... 209
3.2.4.3 Power Management ...................................................................................... 209
3.3 MPU Subsystem Functional Description .............................................................................. 210
3.3.1 Interrupts ......................................................................................................... 210
3.3.2 Power Management ............................................................................................ 210
3.3.2.1 Power Domains ........................................................................................... 210
3.3.2.2 Power States .............................................................................................. 211
3.3.2.3 Power Modes .............................................................................................. 211
3.3.2.4 Transitions ................................................................................................. 215
3.4 MPU Subsystem Basic Programming Model ......................................................................... 216
3.4.1 Clock Control .................................................................................................... 216
3.4.2 MPU Power Mode Transitions ................................................................................ 216
3.4.2.1 Basic Power-On Reset ................................................................................... 216
3.4.2.2 MPU Into Standby Mode ................................................................................. 216
3.4.2.3 MPU Out of Standby Mode .............................................................................. 216
3.4.2.4 MPU Power-On from a Powered-Off State ............................................................ 216
3.4.3 NEON Power Mode Transition ................................................................................ 217
3.4.4 ARM Programming Model ..................................................................................... 217
3.5 Revision History .......................................................................................................... 218
4 Power, Reset, and Clock Management ................................................................................ 219
4.1 PRCM Introduction to Power Management ........................................................................... 220
4.1.1 Goal of Power Management ................................................................................... 220
4.1.2 Power-Management Techniques ............................................................................. 220
4.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 220
4.1.2.2 SmartReflex Adaptive Voltage Control ................................................................. 221
4.1.2.3 Dynamic Power Switching ............................................................................... 222
4
Contents SPRUF98D–October 2009
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
www.ti.com
4.1.2.4 Standby Leakage Management ......................................................................... 223
4.1.2.5 DPS Versus SLM ......................................................................................... 223
4.1.2.6 Combining Power-Management Techniques ......................................................... 224
4.1.3 Architectural Blocks for Power Management ................................................................ 225
4.1.3.1 Clock Domain ............................................................................................. 225
4.1.3.2 Power Domain ............................................................................................ 226
4.1.3.3 Voltage Domain ........................................................................................... 227
4.1.4 Device Power-Management Architecture .................................................................... 227
4.1.4.1 Module Interface and Functional Clocks ............................................................... 229
4.1.4.2 Autoidle Clock Control ................................................................................... 229
4.1.5 SmartReflex Voltage-Control Overview ...................................................................... 231
4.1.5.1 Manual SmartReflex Voltage Control .................................................................. 232
4.1.5.2 Automatic SmartReflex Voltage Control ............................................................... 232
4.2 PRCM Overview ......................................................................................................... 233
4.2.1 Introduction ...................................................................................................... 233
4.2.2 PRCM Features ................................................................................................. 235
4.3 PRCM Environment ...................................................................................................... 236
4.3.1 External Clock Signals ......................................................................................... 237
4.3.2 External Reset Signals ......................................................................................... 238
4.3.3 External Power Signals ........................................................................................ 239
4.4 PRCM Integration ........................................................................................................ 240
4.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 243
4.4.1.1 Power Domain ............................................................................................ 243
4.4.1.2 Resets ...................................................................................................... 243
4.4.1.3 Interrupt Requests ........................................................................................ 244
4.5 PRCM Reset Manager Functional Description ....................................................................... 245
4.5.1 Overview ......................................................................................................... 245
4.5.2 General Characteristics of Reset Signals .................................................................... 245
4.5.2.1 Scope ....................................................................................................... 246
4.5.2.2 Occurrence ................................................................................................ 246
4.5.2.3 Source Type ............................................................................................... 246
4.5.3 Reset Sources ................................................................................................... 247
4.5.3.1 Global Reset Sources .................................................................................... 247
4.5.3.2 Local Reset Sources ..................................................................................... 248
4.5.4 Reset Distribution ............................................................................................... 249
4.5.5 Power Domain Reset Descriptions ........................................................................... 250
4.5.5.1 MPU Power Domain ...................................................................................... 250
4.5.5.2 NEON Power Domain .................................................................................... 251
4.5.5.3 IVA2 Power Domain ...................................................................................... 251
4.5.5.4 CORE Power Domain .................................................................................... 251
4.5.5.5 DSS Power Domain ...................................................................................... 252
4.5.5.6 CAM Power Domain ...................................................................................... 252
4.5.5.7 USBHOST Power Domain ............................................................................... 252
4.5.5.8 SGX Power Domain ...................................................................................... 252
4.5.5.9 WKUP Power Domain .................................................................................... 253
4.5.5.10 PER Power Domain ...................................................................................... 253
4.5.5.11 EMU Power Domain ...................................................................................... 253
4.5.5.12 SmartReflex Power Domain ............................................................................. 253
4.5.5.13 DPLL Power Domains .................................................................................... 254
4.5.5.14 EFUSE Power Domain ................................................................................... 254
4.5.5.15 BANDGAP Logic .......................................................................................... 254
4.5.5.16 External Warm Reset Assertion ........................................................................ 255
4.5.6 Reset Logging ................................................................................................... 255
5
SPRUF98D–October 2009 Contents
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
剩余3548页未读,继续阅读
liangyunfeide
- 粉丝: 0
- 资源: 3
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论2