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书名为 Synthesizable VHDL Design for FPGAs 为英文版
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Synthesizable
VHDL Design
for FPGAs
Eduardo Augusto Bezerra
Djones Vinicius Lettnin
Synthesizable VHDL Design for FPGAs
Eduardo Augusto Bezerra
Djones Vinicius Lettnin
Synthesizable VHDL
Design for FPGAs
123
Eduardo Augusto Bezerra
Djones Vinicius Lettnin
Department of Electrical and Electronic Engineering
Universidade Federal de Santa Catarina
Florianópolis, Santa Catarina
Brazil
ISBN 978-3-319-02546-9 ISBN 978-3-319-02547-6 (eBook)
DOI 10.1007/978-3-319-02547-6
Springer Cham Heidelberg New York Dordrecht London
Library of Congress Control Number: 2013950359
Ó Springer International Publishing Switzerland 2014
This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of
the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or
information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed. Exempted from this legal reservation are brief
excerpts in connection with reviews or scholarly analysis or material supplied specifically for the
purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the
work. Duplication of this publication or parts thereof is permitted only under the provisions of
the Copyright Law of the Publisher’s location, in its current version, and permission for use must
always be obtained from Springer. Permissions for use may be obtained through RightsLink at the
Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt
from the relevant protective laws and regulations and therefore free for general use.
While the advice and information in this book are believed to be true and accurate at the date of
publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for
any errors or omissions that may be made. The publisher makes no warranty, express or implied, with
respect to the material contained herein.
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)
Contents
1 Digital Systems, FPGAs and the Design Flow ............... 1
1.1 Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Field Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . 3
1.3 FPGA Internal Organization. . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Electronic Design Automation and the FPGA Design Flow . . . 8
1.6 FPGA Devices and Platforms. . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Writing Software for Microprocessors and VHDL
Code for FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 Laboratory Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.1 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.2 Laboratory Session . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 HDL Based Designs .................................. 31
2.1 Theoretical Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Laboratory Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1 Laboratory Session . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.2 Going Beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 Hierarchical Design .................................. 43
3.1 Hierarchical Design in VHDL . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Laboratory Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.1 Laboratory Session . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Multiplexer and Demultiplexer .......................... 57
4.1 Theoretical Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Laboratory Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 Laboratory Session . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.2 Version I: Multiplexer in Structural VHDL . . . . . . . . 63
4.2.3 Version II: Multiplexer in Behavioral VHDL. . . . . . . 67
5 Code Converters..................................... 69
5.1 Arrays of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Seven Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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