library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity divCLK is port
(
CLK:in std_logic;
F0:out std_logic;
F1:out std_logic;
F2:out std_logic;
F3:out std_logic;
F4:out std_logic;
F5:out std_logic
);
end divCLK;
architecture clk5 of divCLK is
signal a:natural range 0 to 18;
begin
process(CLK)
begin
if CLK'event and CLK='1' then
case a is
when 18=>
F0<='0';F1<='0';F2<='0';F3<='0';F4<='0';F5<='0';a<=0;
when 14=>
F0<='0';F1<='0';F2<='0';F3<='0';F4<='0';F5<='1';a<=a+1;
when 12=>
F0<='0';F1<='0';F2<='0';F3<='0';F4<='1';F5<='0';a<=a+1;
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