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CMOS VLSI Design, 4th Edition 评分:

For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad
This page intentionally left blank CMOS VLSI Design A Circuits and Systems Perspective Fourth edition Neil H. E. Weste Macquarie University and The University of adelaide David Money harris rvey Mudu colle Addison -Wesle Boslon Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editor in chief: michael hirsch Acquisitions Editor: Matt Goldstein Editorial assistant: chelsea bell Managing Editor: Jeffrey He Com Senior Production Project Manager: Marilyn Lloyd Media Producer: Katelyn Boller Director of Marketing: Margaret Waples Marketing Coordinator: Kathryn Ferranti Senior Manufacturing Buyer: Carol melville Senior media buyer: ginny michaud Text Designer: Susan Raymond Art director. Cover: Linda knowles Cover Designer: Joyce Cosentino Wells/] Wells design Cover Image: Cover photograph courtesy of Nick Knupffer Intel Corporation Copyright C 2009 Intel Corporation. All rights reserved Full Service Vendor: Gillian Hall/The Aardvark Group Publishing Service Copyeditor: Kathleen Cantwell, C4 Technologies Proofreader: Holly Mclean-aldis Printer/binder: edwards brothers Cover Printer: Lehigh-Phoenix Color/Hagerstown redits and acknowledgments borrowed from other sources and reproduced with permission in this textbook appear on appropriate page within text or on page 838 The interior of this book was set in adobe caslon and Trade gothic Copyright O 2011, 2005, 1993, 1985 Pearson Education, Inc, publishing as Addison-Wesley. All ts reserved. Manufactured in the United States of America. This publication is protected by Copyright, and permission should be obtained from the publisher prior to any prohibited reproduc ion,storage in a retrieval system, or transmission in any form or by any means, electronic, mechani- cal, photocopying, recording, or likewise. To obtain permission(s)to use material from this work, please submit a written request to Pearson Education, Inc, Permissions Department, 501 Boylston Street. Suite 900. Boston Massachusetts 02116 Many of the designations by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this boak, and the publisher was aware of a trade mark claim, the designations have been printed in initial caps or all caps Cataloging-in-Publication Data is on file with the Library of Congress Addison-Wesley is an imprint of 10987654321—EB-1413121110 PEARSON ISBN10:0-321-54774-8 ISBN13:9780-321-54774 10 Auril, Melissa, Tamara, Nicky, ocelyn Makayla, Emily, Danika, Dan and simon N W ToJennifer; Samuel, and Abraham D.M. H This page intentionally left blank Contents Preface xxv Chapter 1 Introduction 1.1 A Brief History ... 1.2 Preview 1.3 MOS Transistors 1. 4 CMOS Logic 1. 4. 1 The inverter 9 1.4.2 The NaNd gate 9 1.4.3 CMOS Logic Gates g 1.4.4 The Nor Gate 11 1.4.5 Compound Gates 11 1.4.6 Pass Transistors and Transmission gates 12 1.4.7 Tristates 14 1.4.8 Multiplexers 15 1.4.9 Sequential Circuits 16 1.5 CMOS Fabrication and Layout ....19 1.5.1 Tnycrtcr Cross-Scction 1 9 1.5.2 Fabrication Proccss 20 1.5.3 Layout Design Rules 24 1.5.4 Gate Layouts 27 1.5.5 Stick Diagrams 28 1.6 Design Partitioning 29 1.6.1 Design Abstractions 30 1.6.2 Structured Design 31 1.6.3 Behavioral, Structural, and Physical Domains 3 1.7 Example: A Simple MIPS Microprocessor 1.7.1 MIPS Architecture 33 1.7.2 Multicycle MiPs Microarchitecture 34 1.8 Logic Design 38 1.8.1 Top-Lcvcl Intcrfaccs 38 1.8.2 Block Diagrams 38 1.8.3 Hierarchy 40 1.8.4 Hardware Description languages 40 1. 9 Circuit Design coNtents 1.10 Physical Design ...... 1.10.1 Floorplanning 45 1.10.2 Standard Cells 48 1.10. 3 Pitch Matching 50 1. 10.4 Slice Plans 50 05A 1.10.6 Area Estimation 51 1.11 Design Verification ·::: 1.12 Fabrication, Packaging, and Testing 54 Summary and a look ahead 55 Exercises 57 Chapter 2 Mos Transistor Theory 2.1 Introduction 2.2 Long-Channel I-V Characteristi 4 2.3 C-V Characteristics 68 2.3.1 Simple MOS Capacitance Models 68 2.3.2 Detailed mos Gate c: 2.3.3 Detailed MOS Diffusion Capacitance Model 72 2.4 Nonideal I-V Effects 74 2.4.1 Mobility Degradation and Velocity Saturation 75 2.4.2 Channel Length Modulation 78 2. 4.3 Threshold Voltage effects 79 2.4.4 Leakage 80 2.4.5 Temperature Dependence 85 2.4.6 Geometry Dependence 86 2.4.7 Summarv 86 2.5 DC Transfer Characteristics 87 2.5.1 Static CMoS Inverter dc characteristics 88 2.5.2 Beta ratio effects 90 2.5.3 Noise margin 9 2.5.4 Pass transistor dc characteristics 92 2.6 Pitfalls and fallacies Summary 94 Exercises 95 Chapter 3 CMOS Processing Technology 3. 1 Introduction 3.2 CMOS Technologies 100 3.2.1 Wafer Fornation 100 3.2.2 Photolithography 101 Contents ix 3.2.3 Well and channel formation 103 3.2.4 Silicon Dioxide(SiO2) 105 3.2.5 Isolation 106 3.2.6 Gate Oxide 107 3.2.7 Gate and Source/ Drain formations 108 3.2.8 Contacts and metallization 110 3.2.9 Passivation 112 3.2.10 Metrology 112 3.3 Layout Design Rules .113 3.3.1 Design Rule background 113 3.3.2 Scribe line and Other Structures 116 3.3.3 MOSIS Scalable CMOS Dcsign Rules 117 3.3.4 Micron Design Rules 118 3.4 CMOS Process Enhancements ...119 3.4.1 Transistors 119 3.4.2 Interconnect 122 3.4, 3 Circuit elements 124 3.4.4 Beyond Conventional CMOs 129 3.5 Technology-Related CAD Issues 130 3.5.1 Dcsign Rulc Checking(Drc) 131 3.5.2 Circuit Extraction 132 3.6 Manufacturing Issues 133 3.6.1 Antenna rules 133 3.6.2 Laycr Density Rulcs 1.34 3.6.3 Resolution enhancement rules 134 3.6.4 Metal Slotting Rules 135 3.6.5 Yield Enhancement Guidelines 135 3.7 Pitfalls and Fallacies 136 3.8 Historical Perspective 137 Summary 139 Exercises 139 Chapter 4 Delay 4.1 Introduction 141 4.1.1 Definitions 141 4.1.2 Timing Optimization 142 4.2 Transient Response 143 4.3 RC Delay Mod 146 4.3.1 Effective Resistance 146 4.3.2 Gate and Diffusion Capacitance 147 4.3.3 Equivalent RC Circuits 147 4.3.4 Transient Response 148 4.3.5 Elmore Delay 150

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