Clocking in Modern VLSI Systems

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1 Introduction and Overview Thucydides Xanthopoulos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 The Clock Design Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Some Subjective Milestones in the History of Mi
Series on Integrated Circuits and systems Series editor Anantha chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to Thucydides Xanthopoulos Editor Clocking in modern VLSIS ystems Springer Editor Thucydides Xanthopoulos Cavium networks Marlboro. MA 01752 USA ISSN1558-9412 ISBN978-1-44190260-3 e-ISBN978-1-44190261-0 DOI10.1007978-1-441902610 Springer Dordrecht Heidelberg london New York Library of Congress Control Number: 2009928618 C Springer Science+Business Media, LLC 2009 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. USe in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights Printed on acid-free paper SpringerispartofSpringersCience+businessMedia( ∑τ m MaprapiTo, tO Nix0 xaL tn Mapio-E入vnπ ou uas ENlace oτauo To Margarita, Nicholas and Maria-Helen who joined us half-way through this book reface eo0oτ Es oi av]PGTOL OU HEV ETl0 Juuodoiv e入 i LOL aTeploXeπbov,6e π OOOLEVτo入 oYlouG aUτ Potop0oa THUCYDIDIS HISTORIAE IV: 108 C Hude ed, Teubner, Lipsiae MCMXlll OL avopoToL, anote, ouvelUiSouv va eutloteuovtal eis tnv aepioxEtov e入6ivoπoj0 DuOUV xaL v’dπ oxpoouv OL’a0upeτouU入入Ooo EXELVO tOVπooτ EpYoUV OYKY△I△ OT IETOPIAI△:108 Kaτ a metaboly h入 EUUEplou BEv入oU △.Kax入 udos exo ∑山pv AUny It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject Thucydides(the Peloponnesian War Part D), IV: 108 Thomas Hobbes Trans. Sir w. molesworth ed In The English Works of Thomas Hobbes of Malmesbury, Vol. VIll I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors ex hibited highly innovative clocking systems, always worthy of isscC/Jssc publica- tions and for a while alpha processors were leading the industry in terms of clock performance. I had huge shoes to fill. Obviously, I was overwhelmed, confused and highly confident that I would drag the entire project down. When a few years later VI Preface Carl Harris asked me to do a book on clocking for the Springer Integrated Circuits and Systems Series, I readily agreed with the hope that I could save young and as piring clock designers substantial time and frustration by providing leads and maybe answers to the questions that I had when I was embarking on the Alpha clock design quest. As my choice of opening quotation would suggest, clock design can be a mine field of misconceptions based on little more than a reluctance to apply Kirchhoffs laws, basic constituent relationships, and a little bit of common sense In addition to my personal design experience, the choice of material for this book has been heavily informed by my long tenure in the International Solid-State Circuits Conference(Isscc) program committee. The subjects covered reflect to a large ex- tent the collective interests and foci of both industry and academia with respect to clocking based on ISSCC submissions. The only exception is that there is no cover- age of phase locked loop design since there are a number of recent texts available on this subject matter It is my hope that this book will help engineers and students interested in clock design obtain the appropriate mental models and design viewpoints capture design trends that have appeared over the last few years, and provide a comprehensive list of references for further study. I am indebted to my co-authors for providing preci structured and complete coverage in their respective chapters in addition to main taining a viewpoint that is very up to date and highly reflective of current trends in the industry. I hope that the reader will not find"ungrounded hopes"" magistral arguing” in this book Carl Harris and Katelyn Stanne of Springer deserve special thanks for helping me throughout the preparation of the manuscript. I wish to acknowledge a number of colleagues at Cavium Networks for their helpful and stimulating discussions and excellent feedback: Scott Meninger, Ethan Crain, David Lin, and Suresh Balasubra manian.I would like to thank my bosses at Cavium Networks Anil Jain and Syed Ali for building a great semiconductor company from the ground up and an excellent working environment that fosters creativity and innovation in addition to maintaining a sharp focus on product development and company value. I would especially like to thank Anil Jain for entrusting me with the alpha clocking project while being my boss at Compaq Computer which helped me acquire the background and skills nec- essary to produce this book. Above all, I would like to thank my wife Margarita not only for putting up with my constant working on this book but also for typesetting the entire manuscript in LATEX and retouching figures as needed. I could not have done this without her Boston massachusetts TX December 2008 Contents 1 Introduction and Overview Thucydides Xanthopoulos 1.1 The Clock Design Problem 1. 2 Some Subjective Milestones in the History of Microprocessor clocking 1. 2.1 Integrating the PLL 1.2.2 Clock Distribution moves to the forefront The dawn of the ghz race 1.2.3 Delay Lock Techniques 2444555 1.2.4 Exploiting Inductance for Oscillation and Distribution 1.2.5 Variable Frequency(and Voltage 1.2.6 Frequency Increase(or Supply lowering) Through Resiliency 1.3 Overview of this book References 2 Modern Clock Distribution Systems Simon tam 2.1 Introduction 2.2 Definitions and Design requirements 10 2.2.1 Setup and Hold Timing Constraints 2. 2.2 Clock Attributes Static and Dynamic Clock Uncertainties ...14 Distribution dela y Duty Cycle 19 2.2.3 Clock Distributio 2.3 Clock Distribution Topologies 21 2.3.1 Unconstrained Tree 21 2.3.2 Balanced Tr 23 2.3.3 Central spine 25 2.3.4 Spines with Matched B 2.3.5 Grid 26 2.3.6 Hybrid Distributi 29 2.4 Microprocessor Clock Distributions 30 Contents 2.5 Clock Design for Test and Manufacturing 36 2.5.1 Global and Local Clock Compensations 36 2.5.2 Global Clock Compensation Architecture 37 2.5.3 Local Clock Compensation Architecture 43 2.6 Elements of Clock Distribution Circuits 2.6.1 Clock Duty Cycle 2.6.2 Power Supply 47 2.7 Clock DFX Techniques 48 2.7.1 Optical Probing 48 2.7.2 On-Die Measurement 2.7.3 Locating Critical Path 52 2.7.4 On-Die-Clock Shrink 52 2. 8 Multiclock domain distribu 54 2.8.1 Multicore Processor Clock distribution 2.9 Future Directions 58 2.10 Conclusion 58 Refe 59 3 Clocked Elements James warnock 67 3.1 Introduction 67 3.2 CSE Design Issues 68 3.2.1 Latency 3.2.2 Hold Time 3.2.3 Power..... 3.2.4 Scan Design for CSEs 3.3 Static Latch Designs 72 3.3.1 Master-Slave latches 3.3.2 Two-Phase Level-Sensitive Latches 76 3.3. 3 Pulsed-Clock Static Level-Sensitive Latches 3.4 Flip-Flop Designs 3.4.1 Sense-Amp Style Flip-Flop 3.4.2 Hybrid Latch Flip-Flop 82 3.4.3 Semi-Dynamic Flip-Flop ..83 3.5 Test and Debug Considerations ....85 3.6 CSE Design for Variability 88 3.6.1 Variability-Induced Frequency degradation 88 3.6.2 Variability-Induced Functional Failures............ 89 3.7 Reliability Issues 91 3.7.1 Soft error rate considerations 3.7.2 End of Life Considerations for CSE Deso 91 93 3. 8 Conclusion Acknowledgements 96 References 97

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