i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual

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i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual(IMX6D/Q 多媒体应用处理参考手册),一共74个章节,涵盖IMX6D/Q芯片内部所有接口、总线、寄存器的功能与配置。
Contents Section Number Title Page Chapter 1 Introduction 1.1 About This document 1.1.1 Audience 1.1.2 Organization.…… .200 1.1.3 Suggested reading 200 1. 1. 3.1 General Information ...............................................................................................................200 1.1.3.2 Related Documentation 200 1.1.5 Register Access........... .202 1. 1. 5. 1 Register Diagram Field Access Type Legend 202 1.1.5 Register macro us 20 Signal c 1.1.7 Acronyms and Abbreviations 204 1.2 Introducti .205 1.3 Target Applications 1. 4 Features 206 1. 5 Architectural overview +++++++·++++“+++ 210 1.5.1 Block diagram ……210 1.5.1.1 Simplified Block diagram.…… 1.5.2 Architectural partitioning………… …………211 1.5.3 Endianness Support.… ········:·…··…······· 213 1.6 Memory Interfaces 214 Chapter 2 Memory Maps 2.1 Memory system overview 2.2 ARM Platform Memory Map..... 215 2.3 DDR mapping to MMdc controller ports 221 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Freescale semiconductor Inc Preliminary -Subject to Change Without Notice Freescale Confidential Proprietary Section Number Title age 2.4 DMA Memory Map.... 222 Chapter 3 Interrupts and DMA Events 3.1 Overview 3.2 AP Interrupts 22 3.3 SDMA EVent Mapping.....,,,…,.……230 Chapter 4 External Signals and Pin Multiplexing 4.1 Introduction ··1 ······ 233 4.2 External Signals 233 Chapter 5 External Memories 5.1 Overview 429 5.2 Multi-Mode dDr Controller (MMDC) 429 5.2.1 DDR Controller features 430 5.2.2 Raw NaND-Flash Controller (GPMI, BCH40 and APBH DMa) 431 5.2.2 AND Interface 432 5.2.2.2 NAND control .……1433 5.2.2.3 Internal interface 433 5.2.2.4 APBH-DMA 433 5.2. 2.5 ECC-BCH 433 5.3 EIM- PSRAM/NOR-Flash controller 434 5.3 EIM Feature 434 5.3.2 Boot scenarios………… 435 5.3.3 OneNand Restrictions/limitations 435 Chapter 6 System Debug 6.1 Overview ““““““+““““ 437 6.1.1 Introduction ····:······ 437 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 4 Preliminary -Subject to Change Without Notice Freescale semiconductor Inc Freescale Confidential Proprietary Section Number Title age 6.2 1.MX dUal/6Quad and Cortex-A9 Core Platform Debug Architecture 438 6.2.1 Debug Features 438 6.2.2 Debug System components listing 439 6.2.3 Embedded Cross Triggerrin.……… 6.2.3.1 CroSs-Trigger Matrix(CTM) 6.2.3.2 Cross-Trigger Interface(CTD 41 6.2.4 CoreSight Trace Port Interface (TPlU) 41 6.2.5 i.MX6Dual6Quad-Specific SJC Features 441 6. 2.5.1 JTAG Disable mode 441 6.2.5.2 PROD ID& JTAG ID.…………442 6.2.6 System JTAG Controller-SJC 4412 6.2.7 System JTAG Controller Main Feature 442 6.2.8 SCJ TAP Port 43 6.2.9 SJC main blocks .43 6.3 Peripherals Debug features 43 6.3.1 Smart DMA (SDMA) Core 444 6.3.1.1 SDMA On Chip Emulation Module(OnCE) Feature Summary 6.3.1.2 Other SDM Debug Functionality..........…….…………45 6.3. 1 3 SDMA ROM Patching. 446 6.3.2 DDR Controller debug 446 6.3.3 IPU 446 64 Debug Signals Visibility via the IOMUX.…… 自面面面 …4-46 6.5 Miscellaneous… 447 6.5.1 DTCP Key Handling 447 6.5.2 Clock/ reset/ power 147 6.6 Supported tools… 447 Chapter 7 System Boot 7.1 Introduction.… 449 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Freescale semiconductor Inc Preliminary- Subject to Change Without Notice 5 Freescale Confidential Proprietary Section Number Title age 7.2 Boot modes 7.2.1 Boot mode pin Settings 451 7.2.2 High Level Boot Sequence….… 451 7.2.3 Boot From Fuses Mode (BOot_ mode[l: 0]=0b00) 452 7.2.4 Serial Downloader Mode(BOOT_MOdE[l: 0]=0b01) 453 7.2.5 Internal Boot Mode (bOot_ mode[l: 0]=0b10 454 7.2.6 Boot Security Settings 454 7.3 Device Configuration 45 7.3.1 Boot eFUSE Descriptions ·····*:···················;““·· 455 7.3.2 GPIO Boot Overrides. 7.3.3 Device Configuration Data................................459 7.4 Device initialization 459 7.4.1 Internal ROM/RAM Memory Map 7.4.2 Boot block activation 460 7.4.3 Clocks at Boot Time 461 7.4.4 Enabling MMU and Caches 1464 7.4.5 Exception Handling 64 7.4.6 Interrupt Handling during boot 465 7.4.7 Persistent bits ..465 7.5 Boot Devices (Internal Boot) 466 7.5.1 NoR Flash/Onenand using elm interface 467 7.5.1.1 NOR Flash Boot Operation 467 7.5.1.2 OneNAND Flash Boot Operation 467 7.5.1.3 IOMUX Configuration for eIm devices 468 7.5.2 NAND Flash 470 7.5.2.1 NaNd eFUSe Configuration 470 7.5.2.2 NAND Flash Boot Flow and Boot Control Blocks(BCB)...... .471 7.5.2.3 Firmware Configuration Block 474 7.5.2. 4 Discovered Bad Block Table 476 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Preliminary -Subject to Change Without Notice Freescale semiconductor Inc Freescale Confidential Proprietary Section Number Title age 7.5.2.5 Bad block handling in the rom. ····:········“·*4··:·····*··· 477 7.5.2.6 Toggle Mode DDR NAND Boot 478 7.5.2.6.1 GPMI and BCH Clocks Configuration.……….….….….….….……….1478 7.5.2.6.2 Setup dma for ddr transfers 7.5.2.6.3 Reconfigure Timing and Speed Using Values in FCB......479 7.5.2.7 Typical NAND Page Organization......….…..…479 7.5.2.7.1 BCH ECC Page Organization.. 480 7.5.2.7.2 Metadata 481 7.5. 2 8 IOMUX Configuration for nand 481 7.53 Expansion device 1482 7.5.3.1 Expansion Device 7.5.3.2 MMC and eMMC Boot 485 7533 SD. esd and sdXc. 7.5.3. 4 OMUX Configuration for Sdmmc 493 7.5.4 Hard disk and ssd 494 7.5.4.1 Hard Disk and SSD eFUSE Configuration 494 7.5.4.2 IOMUX and Timing Configuration fOr SATA……….…….….….…….…..495 7.5.4.3 Redundant boot Support for Hard Disk and SSD …495 7.5.5 Serial rom through spi and i2c 497 7.5.5.1 Serial ROM eFUSE Configuration 7.5.5.212 C Boot. 7.5.5.2.1 I2C IOMUX Pin Configuration 500 7.5.5.3 ECSPIB0Ot.....................1.….500 7.5.5.3.1 ECSPI IOMUX Pin Configuration 502 7.6 Program Image...… 7.6.1 Image Vector Table and Boot Data.. 503 7.6.1.1 Image Vector Table Structure 50 7.6.1.2 Boot Data Structure 505 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Freescale semiconductor Inc Preliminary- Subject to Change Without Notice Freescale Confidential Proprietary Section Number Title age 7.6.2 Device Configuration Data dCD)....... 7.6.2.1 Write data Command 506 7.6.2.2 Check data Command 7.6.2.3 NOP Command 7. 6. 2. 4 Unlock Command. ......................................................................................510 7.7 Plugin Image …510 7. 8 Serial Downloader 511 7.8.1 USB .512 7. 8.1.1 USB Configuration Details....................... 513 7. 8.1.2 IOMUX Configuration for uSB .514 7.8.2 rial Download protocol 514 7.8.2.1 SDP Command 514 7.8.2.1.1 READ REGISTER 515 7.8.2.1.2 WRITE REGISTER 515 7.8.2.1.3 WRITE FILE ∴…516 7.8.2.1.4 ERROR STATUS...................................517 7.8.2. 1.5 DCD WRITE .518 7.8.2.1.6 JUMP ADDRESS.… 519 7.9 Recovery Devices 519 7.10 USB Low Power boot 520 7.11 High Assurance Boot(HAB).…… 521 7.11.1 ROM Vector Table addresses,wwO..522 Chapter 8 Multimedia 8.1 Video Graphics Sub System .525 8.1.1 Display outputs 526 8.1.2 Video input...... 527 8.1.3 Synchronization Mechanisms. 529 8.1.3.1 Synchronization between the voA and the iPu. 529 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Preliminary -Subject to Change Without Notice Freescale semiconductor Inc Freescale Confidential Proprietary Section Number Title age 8.1.4 Supported Applications........... 8.2 Image Processing Unit(IPU) ““““““ 532 8.2.1 IPU External Ports. ..............................................................................................534 8.2.1.1 Camera Ports 535 8.2.1.2 Display Ports.......….….….….….….….….…….….…..536 8.2.1.2.1 Access modes 8.2. 1.2.2 Synchronous Access 536 8.2.1.2.3 .synchronous Access ..... 537 8. 2.1.2, 4 Interface details.............537 8.2.1.2.5 Connecting To Display devices............... 538 8.2.2 Pr rocessing.………∴∴∴……………… .………538 8.2.2.1 Display Processor ( DP) 540 8.2.2.2 Video De-Interlacer (VDIC)........... 8.2.2.3 Image Converter (Ic)... 541 8.2.2.4 Image Rotator (rT) 542 8 2.3 Automatic Procedures 542 8.2.4 Further Changes in IPUv3H vS. IPUV3M 543 8.3 LVDS Display Bridge(LDB ).... 543 8.3.1 LDB Overview 54 8.3.2 LDB External ports 544 833 Input Parallel Display Ports.………… 544 8.3.3.1 Output LVds Ports …545 8.3.3.2 Control Signals..... 545 8.4 Video Data Order Adapter (VDOA) 546 8.4.1 VDOA Interfaces 8.4.2 VOA Data path 546 8.4.2.1 Input 546 8.4.22 Output.… 546 8.4.3 Control 547 MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 Freescale semiconductor Inc Preliminary -Subject to Change Without Notice Freescale Confidential Proprietary Section Number Title age 8.5 Display Content Integrity Checker (DCIC) 547 8.5.1 DCIC Interfaces 548 8.5.2 DCIC Data path 8.5.3 Configuration parameters.…… 549 8.54 System Considerations 549 8. Video processing unit(VPUV6).…..……………50 8.6.1 Basic structure 862 Feature Summary…… 8.7 OpenGL ES3 D Graphics Processing Unit(GPU3Dv4)……… 553 8.7.1 OpengL Overview...….….….….….….….… 553 8.7.2 Opengl Features......................553 8.7.3 Opengl Block Diagram 54 8.7.4 Opengl Performance.… 8.7.5 Opengl Software… 555 8.82 D Graphics Processing Unit(GPU2Dv2).......………555 8.8.1 2D Features 555 8.8.2 2d Block diagram 88.3 2D Performance 2557 8.8.4 2D Software 57 8.9 Vector Graphics Processing Unit(GPUVGv2) 557 8.9.1 Vector Graphics Overview. 558 89.2 Vector Graphics Features 558 89.3 Vector Graphics Performance..... .…..…………59 89.4 Vector Graphics Software 559 8.10 HDMI- HD Multimedia interface transmitter 559 8.10.1 HDMI Introduction 559 8.10.2 Features …“ 561 8.11 y/ Sensor mipi interfaces…… 562 8.11.1 Introduction MX 6Dual/6Quad Multimedia Applications Processor Reference Manual, Rev. C, 1/2012 10 Preliminary -Subject to Change Without Notice Freescale semiconductor Inc Freescale Confidential Proprietary

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