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Xilinx Virtex2pro的user guide 评分:

xilinx官方的V2P板子的用户使用说明书
Contents Chapter 1: XUP Virtex-l Pro development system Features General Description. ·········· ,,,,,14 Block Diagram ,,,,,,,14 Board Components 14 Virtex-II Pro fPga 15 Power Supplies and FPGA Configuration∴… 16 Multi-Gigabit Transceivers 17 System ram ,,,,,,,17 System ace Compact Flash Controller Fast Ethernet Interface ,,17 Serial Ports 17 User LEDs, Switches, and Push buttons .....18 Expansion Connectors 18 XSGA Output 18 ac97 Audio codec 垂 18 CPU Trace and Debug Port 着垂 18 USB 2 Programming Interface Chapter 2: Using the System Configuring the power supplies ·· ..19 Configuring the FPGA ,,,,,,∴,,20 Clock generation and distribution 2 Using the DIMM Module DDR SDRaM 24 Using the XSGA Output 34 Using the ac97 Audio COdEC and Power Amp 39 Using the LEds and Switches ..43 Using the Expansion headers and digilent expansion connectors Using the CPu Debug Port and CPU reset USing the Serial Ports Using the Fast Ethernet Network Interface Using System ACE Controllers for Non-Volatile Storage 65 Using the multi-Gigabit Transceivers UGo69(1.0) March8,2005 Www.xuinX.com XUP Virtex-ll Pro Development System Appendix A: Configuring the FPGa from the Embedded USB Configuration Port Appendix B: Programming the Platform FLASH PROM User Area Appendix C: Restoring the Golden FPGA Configuration Appendix D: Using the Golden FPGA Configuration for System Self- Test Hardware-Based Tests .98 Power Supply and RESET Test 98 Additional hardware Required ∴.........98 Test Procedure ,,,,,98 Clock, Push Button, DIP Switch, LED, and Audio Amp Test 99 Additional hardware Required Test Procedure SVGa Gray scale test Additional hardware required Test procedure SVGA Color Output Test 100 Additional Hardware required Test procedure 100 Silicon Serial Number and Ps/2 Serial Port Test 101 Additional hardware required Test Procedure 101 Processor-Based Tests Additional hardware required ......102 MGT Serial ATA Test 102 Additional Hardware Required ........102 EMAC Web Server Test 106 Additional Hardware required EMAC Web Server Test Procedure 106 AC97 Audio Test Additional Hardware required 109 Digital Passthrough Test Procedure ·:.· 109 FIFO Loopback Test Procedure ,,,,,,,,110 Game Sounds Test procedure ..,,...,,.,..110 System ACE Test System ACE Test Procedure 11 DDR SDRAM Test ,,,,,112 Additional Hardware Required 112 Test procedure 112 Expansion port Test 113 Additional Hardware required ,,,,,,,,,,,,,,,,,113 Test procedure XUP Virtex-ll Pro Development System Www.xuinX.com UGO69(1.0) March8,2005 Appendix E: User Constraint Files UCF Appendix F: Links to the component Data Sheets FPGA Related Documentation 137 Configuration So 137 DDR SDRAM Modules 37 Audio processing ..,,,,,138 XSGA Video Output 138 Ethernet Networking 138 Power Supplies∴ ,138 UGo69(1.0) March8,2005 Www.xuinX.com XUP Virtex-ll Pro Development System XUP Virtex-ll Pro Development System Www.xuinX.com UG069(v1.0)March 8, 2005 Figures Chapter 1: XUP Virtex-ll Pro development system Figure 1-1: XUP Virtex-II Pro Development System Block Diagram Figure 1-2: XUP Virtex-II Pro Development System Board Photo .,15 Figure1-3: 1O Bank Connections to Peripheral devices………………… ..16 Chapter 2: Using the System Figure 2-1: Typical Switching Power Supply 19 Fure2-2: MGT Power∴…………… ...20 Figure 2-3: Configuration Data Path 22 Figure 2-4: External Differential Clock Inputs 24 Figure 2-5: Alternate Clock Input Oscillator Figure 2-6: Definition of Start and Stop Conditions 25 Figure 2-7: Acknowledge Response from Receiver 26 Figure 2-8: EEPROM Sequential Read 26 le2-9: EEPROM Write∴ Figure 2-10: Clock Generation for the DDR SDRAM .29 Figure 2-11: XSGA Output 36 Figure 2-12: AC97 Audio Codec ·· Figure 2-13: Audio Power Amplifier ..42 Figure 2-14: Expansion Headers Figure 2-15: CPU Debug Connector Pinouts Figure 2-16: RELOAD and CPU RESET Circuit ,,.,,60 Figure 2-17: RS-232 Serial Port Implementation Figure 2-18: PS/2 Serial Port Implementation ,62 Figure 2-19: 10/100 Ethernet Interface Block Diagram Figure 2-20: SMA-based MGT Connections Figure 2-21: 1.5 Gb/s Serial data Transmission over 0.5 meter of SATA Cable Figure 2-22: 1.5 Gb/s Serial Data Transmission over 1.0 meter of SATA Cable 70 Appendix A: Configuring the FPGa from the Embedded USB Configuration port Figure A-1: Device Manager Cable Entry 72 Figure A-2: iMPACT Cable Selection Drop-Down Menu Figure A-3: iMPACT Cable Communication Setup Dialog Figure A-4: Initializing the jTAG Chain Figure A-5: Properly Identified TAG Configuration Chain Figure A-6 Assigning Configuration Files to Devices in the JTAG Chain......75 Figure A-7: Assigning a Configuration File to the FPGA 76 UGo69(1.0) March8,2005 Www.xuinX.com XUP Virtex-ll Pro Development System igure A-8: Programming the FPGA 76 Appendix B: Programming the Platform FLASH PROM User Area Figure B-1: Operation Mode Selection: Prepare Configuration Files Figure B-2: Selecting PROM File Figure B-3 Selecting a PROM with Design Revisioning Enabled Figure B-4: Selecting an XCF32P PROM with Two Revisions Figure B-5: Adding a Device File Figure B-6 Adding the Design File to Revision 0 Figure B-7: iMPACT Startup Clock Warning Figure B-8: Adding the Design File to Revision 1 Figure B-g: Generating the MCs File Figure B-10: Switching to Configuration Mode 82 Figure B-11: Initializing the jTAG Chain Figure B-12: Assigning the MCs File to the PROM ,.,,,,,83 Figure B-13: Programming the PROM Figure B-1: PROM Programming Options..……∴ Figure B-15: iMPACT PROM Programming Transcript Window 85 Appendix C: Restoring the Golden FPGA Configuration Figure C-1: Operation Mode Selection: Configure Devices Figure C-2: Selecting Boundary Scan Mode Figure C-3: Boundary Scan Mode Selection: Automatically Connect to the Cable and identify the itag chain 90 Figure C-4: Assigning New PROM Configuration File Figure C-5: Erasing the Existing PROM Contents Figure C-6: Transcript Window for the erase command Figure C-7: Selecting the Program Command Figure C-8: PROM Programming Options 94 Figure C-9: iMPACT PROM Programming Transcript Window 95 Appendix D: Using the Golden FPGA Configuration for System Self- Test Figure D-1: XUP Virtex-II Pro Development System BIST Block Diagram ..97 Figure D-2: Built-In Self-Test Main Menu 102 Figure D-3: Testing the sata O HOST to SAtA 1 TARGET Connection...... 103 Figure D-4: Testing the sata 2 hoSt to Sata 1 TARGET Connection Figure D-5: Selecting the SATA Port Tests 104 Figure D-6: Selecting the Specific SATA Port to Test ,,,,,,,104 Figure D-7: Resetting the MGTs ,,,,,,104 Figure D-8: No Link Established Error Message 105 Figure D-g: SATA Test Running Figure D-10: SATA Loopback Test PASSED XUP Virtex-ll Pro Development System Www.xuinX.com UGO69(1.0) March8,2005 Figure D-11: Specifying IP Address for XUP Virtex-lI Pro Development System Figure D-12: Web Server Running 107 Figure D-13: Web Server Display ..108 Figure D-14: Web Server Stopped Figure D-15: Selecting the Specific AC97 Audio Test 109 Figure D-16: Digital Passthrough Test Completion Figure D-17: FIFO Loopback Test Completion Figure D-18: Game Sounds Test Completion 111 Figure D-19: System ACE Test Completion 111 Figure d-20: DDR SDRAM Test Completion 113 Figure D-21: Confirming Start of the Expansion Port Walking Ones Test 114 Appendix E: User Constraint Files(UCF) Appendix F: Links to the Component Data Sheets UGo69(1.0) March8,2005 Www.xuinX.com XUP Virtex-ll Pro Development System XUP Virtex-ll Pro Development System Www.xuinX.com UG069(v1.0)March 8, 2005

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