innovus user guide

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innovus 15.2 user guide innovus 15.2 user guide innovus 15.2 user guide innovus 15.2 user guide
Innovus User Guide Table of contents Contents About this manual 33 Audience 33 How This manual ls organized 33 Conventions Used in this manual 34 Related documents 35 Additional Learning Resources 36 38 Product and licensing Information 38 Overview 38 Innovus System Products and product options 39 Innovus 39 Virtuoso digital Implementation 43 First Encounter 44 Product Options 46 Migration and Upgrade 49 Migration and Upgrade for Base Products 50 Migration and Upgrade for Product Options 51 Licensing Information 51 Licensing Terminology 51 Dynamic Licensing 5 Multi-CPU Licensing 54 Optional License Requirement for 10/20/32nm Nodes 55 56 Flows 56 Design Implementation Flow 57 Introduction 59 Recommended Timing Closure Flow 59 November 2015 Product version 15.20 Innovus User Guide Table of contents Software 60 Foundation flow 60 Data Preparation and validation 61 Flow Preparation 68 Pre-Placement Optimization 71 Floorplanning and Initial placement 72 GigaPlace 76 Clock Tree Synthesis 82 PostcTS Optimization 84 Detailed routing 88 PostRoute Optimization 91 Chip Finishing 96 Timing sign off 97 Final Timing Analysis and Optimization using Tempus/Quantus 98 Additional resources 99 Hierarchical and Prototyping Flow 100 Introduction 100 Top-down and Bottom-up Hierarchical Methodologies 102 Hierarchical Floorplan considerations 104 Hierarchical Partitioning Flow and Capabilities 106 Chip Planning 109 Supporting Giga- Scale Designs in Planning stage 122 Top-level Timing Closure 122 Chip assembly 124 3 128 Infrastructure Related capabilities 128 Getting Started 129 Product and Installation Information 129 Setting the Run-Time Environment 130 Temporary File Locations 131 Open Access 131 November 2015 Product version 15.20 Innovus User Guide Table of contents Launching the console 131 Tab Completing Command Names, Parameter Names, Global Variable Names and Enum Values 132 Command-Line editing 134 Setting preferences 138 Starting the Software 138 Interrupting the Software 139 Using the log file viewer 141 Accessing Documentation and Help 142 Customizing the User Interface 150 Overview 150 Creating a New menu 151 Modifying an EXisting Menu 152 Adding a New Toolbar and Toolbutton 155 Querying and Configuring Interface Elements 157 Accelerating the Design Process By Using Multiple-CPU Processing 159 Overview 159 Running Distributed Processing 162 Running Multi-Threading 162 Running Superthreading 163 Memory and run Time control 163 Checking the Distributed Computing Environment 165 Setting and Changing the License Check-Out Order 165 Limiting the multi-CPU License Search to Specific Products 166 Releasing licenses before the session ends 166 Controlling the Level of Usage Information in the log File 166 Where to Find More Information on Multi-CPU Licensing 167 Data Preparation 167 Generating a Technology file 168 Preparing Physical Libraries 168 Unsupported LEF and DEF Syntax 169 November 2015 Product version 15.20 Innovus User Guide Table of contents Generating the l/O Assignment File 173 Preparing Timing Libraries 197 Encrypting libraries 197 Preparing Timing Constraints 197 Preparing Capacitance Tables 198 Preparing data for delay calculation 198 Preparing Data for Crosstalk Analysis 198 Checking designs 198 Preparing Data in the Timing Closure Design Flow 199 Converting iPRT Format to LEF 199 Importing and Exporting Designs 199 Overview 201 Verifying Data before Importing a Design 202 Preparing the Design Netlist 202 The init _design Import Flow 202 Importing Designs using the GUI 207 Loading a previously saved global variables file 209 Handling verilog Assigns 209 Configuring the Setup for Multi-Mode Multi-Corner Analysis 209 Saving designs 223 Loading and Saving Design Data 225 Converting an Innovus Database to gDsll Stream or OaSIS Format 228 About the gDsll Stream or OASiS Map File 234 Updating Files During an Innovus Session 244 SKILL to TCL Mapping 245 248 Design Planning Capabilities 248 Floorplanning the design 249 Overview 251 Common Floorplanning Sequence 251 Viewing the Floorplan 252 November 2015 Product version 15.20 Innovus User Guide Table of contents Module Constraint Types 254 Grouping Instances 260 Creating and Editing Rows 265 Using Vertical Rows 266 Using Multiple-height Rows 269 Performing I/O Row Based Pad Placement 280 Editing pins 287 Running Relative Floorplanning 297 Saving and Loading Floorplan Data 300 Snapping the floorplan 301 Resizing the floorplan 302 Checking the Floorplan 313 FinFET Technology 315 Using Structured Data Paths 320 Overview 320 Benefits of Using SDP 321 General SDP Flow 323 Support for high-Speed Flip Flop columns 324 SDP Placement Flow 325 Implementing SDP Capability 331 SDP Relative Placement File 332 Aligning sdps by pins 344 Setting sdP Options 346 Optimizing a Design with SDPs 348 Checking SDP Placement 350 Bus Planning 351 Overview 351 Bus planning flow in Innovus 352 Creating a Bus Guide 353 Moving and stretching a Bus guide 362 Cutting, Splitting and merging Bus Guides 362 November 2015 Product version 15.20 Innovus User Guide Table of contents Customizing the Bus guide Display 364 Saving and restoring bus guide Information 366 Verifying Bus Guide 366 Limitations of Bus Planning 366 Power Planning and Routing 368 Overview 368 Before You begin 369 Results 370 Loading, Saving, and Updating Special Route 370 Global Net connections 370 Creating a ring with User Defined coordinates 372 Fixing LEF Minimum Spacing Violations 373 Adding Stripes to Power Domains 373 Adding Stripe in Multi-CPU mode 375 5 376 Design Implementation Capabilities 376 Low Power design 377 Overview 379 Power Domain Shutdown and Scaling 380 Support for the Common Power Format (CPF 381 Support for IEEE1801 384 Flow Special Handling for Low Power 390 Multiple Supply Voltage Top-Down Hierarchical Flow 409 Example of block-Level cP f generated by Innovus 415 EXample of Top-Level CPF Generated by Innovus 418 Multiple Supply voltage Bottom-Up Hierarchical Flow 423 Leakage Power Optimization Techniques 425 Power Shutdown Techniques 429 Power Switch Optimization 454 Power Switch Prototyping 456 Placing the design 465 November 2015 Product version 15.20 Innovus User Guide Table of contents Overview 466 Loading a design 466 Preparing for placement 467 Guiding placement with blockages 467 Adding Well-Tap cells 469 Adding End-Cap Cells 470 Placing Spare Cells and Spare Modules 472 Adding Padding 479 Placing Standard cells 482 Running placement in multi- CPU Mode 483 Checking Placement 486 Adding filler cells 488 Placing Gate Array Style Filler Cells for Post-Mask ECO 489 Adding Decoupling Capacitance 490 Adding Logical Tie-Off Cells 491 Saving placement data 491 Specifying and Placing JTAG and Other Cells Close to the lOs 491 Optimizing and reordering scan chains 492 Clock Tree Synthesis 505 The Clock Tree Synthesis Engines 507 Overview 508 Flow and Quick start 510 Configuration and method 515 Concepts and clock Tree Specification 527 Reporting 549 CCOpt Clock Tree Debugger 559 Additional Topics 569 CCOpt Property System 575 Migrating from FE-CTS 579 Legacy FE-CTS Flow 581 Legacy FE-CTS Capabilities 586 November 2015 10 Product version 15.20

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