Intel_Romley_PDG_1.1

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The Romley Platform Design Guide (PDG) documents Intel’s design recommendations and guidelines for systems built on the Romley Platform. The PDG provides motherboard routing and layout guidelines as well as other platform design considerations such as power delivery, thermal and system management
intel 35 1.1 Romley Platform Overview 36 39 2. 1 Romley board Stack-Ups 39 2.1.1 Romley platform 6-Layer 1080 Stack-up orm 8-Layer 1080 Stack-up 2. 1.3 Romley platform 10-Layer 1080 Stack-up 40 2.1.4 Romley platform 14-Layer 1080 Stack-up 42 2.2 Romley Platform Common Field Solved Impedance Table 43 2.3 High-Speed PCB Loss.. 1国■ 44 2.3.1 High Speed Differential Loss Magnitude requirement. . 2.3.2 Insertion Loss Measurement recommendations ...m..,.w... 44 2.3.3 Humidity Impact on loss 日■量1面画1面面n1画11面量日日1 47 2. 4 Component Quadrant Layouts 48 2.4.1 Sandy Bridge-EP/EP 4s Processor Quadrant Layout. .49 Sandy bridge-EN Processor Quadrant Layout. 50 2 Patsburg PCh Quadrant Layout 51 53 3.1 Length Matching Requirements 54 3.2 Routing Clearance from vertical Features . aIIm. _画1 64 3.3 Controlling voltage Regulator ( ∴64 3. 4 Reference plane 70 3.5 Escape Routing 3.6 Routing th h pin field 3.7 Layer transitions and via stubs....................................80 3.8 Connector Routing guideli 86 3.9 Routing Under Connector Foot- print.……………,…,………… 88 3.10 AC Coupling Placement 3. 11 PCIe and DMI2 General Routing guidelines............ ..90 2 Signal integrity Guideling 92 97 4.1Inte@ Quick Path Interconnect and Memory Interface Clocking………………97 4.1.1 PCI EXpress* Clocking 97 4.1.2 I/O Clocking and Miscellaneous Clocking….…….………97 4.2CK420BQ,CK-MNG, and dB1900 Z Operational Settings.………,,…,…,.9 4.3 General Routing Guidelines for Clocks….…,…,……,…,,,…,,,…,100 4.3.1 Reference Clock Routing Rules.......,..... ∴100 4.3.2 Length Matching and Common Buffer Guidelines................ 102 4.4 Reference Board Topology Examples 102 4.4.1 Cascaded clock Topologies 102 4.4.2 PCI Express Reference Clock Topologies 104 4.4.3 Intel@R QPI Reference Clock Topologies 114 4.4.4 Other Reference Clock Topologies…………………………………………………,116 4.5CK-MNG/CK-MNG+ Clock Synthesizer.…………,…,…,…,……… 122 4.6 Single Ended Reference Clock Signals and Topologies 122 4.6.1 50 MHz RMII Reference Clock Topology... 123 4.6.2 CLK48 MHz Clock Group.......... 123 4.6.3 Topology for CLK48 ∴124 4.6.4 CLK33 Clock group……… 124 4.6.5 Topology for CLK33 ∴.125 4.6.6 Sharing 33-MHz Clocks. 126 Reference number: 441694, Revision 1.1 intel 4.6.7 25 MHz Reference Clock Topology..........................127 4.7 CLK14 Group .128 4.7.1 Single Load Topology for CLK14 128 4.7.2 Two Load Topology for clK14 129 4.8 Clock Driver Decoupling. . 4, Clock power delivery… 130 4.10 CK420 BQ Power Plane Filtering ∴130 4.10.1 VDD Plane Filtering . 130 4.10.2 VDDa Plane Filtering,,,,,,,,,,,,,,,,,,,,…130 4,10.3 VDD 48 Plane filte 31 4.11 DB1900Z Power Plane Filtering........... 131 4.12 EMI Constraints 132 4.13 Crystal Recommendation for CK420BQ………,…,…,………132 4.13.1 Crystal Loading………,,…,…,…,… ∴132 4.13.2 Crystal Placement and Connectivity.... .133 .135 5. 1 Sandy bridge-EP/EP 4S CPU Socket ID Strapping 135 5.2 Sandy Bridge-EN/EP/EP 4s Processor Intel R QPI 136 5.2.1 Intel QPI Layout Topologies 138 5.2.2 Intel(R QPI Routing guidelines ..,.... 146 5.2.3 Intel@ QPI Signal Integrity Notes.......... 149 5.2.4 Intel@ QPI Miscellaneous Circuits……,,…,,…,,,…,,150 5.3 CPU Miscellaneous Signals Overview. ,151 5.3.1 CPU Miscellaneous Signals Routing Guidelines 154 5.3.2 ERROR M[2:0] and Cat err N Topology.……,…,,…,,,,155 5.3.3 CPU ONLY RESET Topology....... 157 5.3.4ITID_ N and SKToCC_N Topology…… 159 5.3.5 PMSYNC Topology and guidelines....... ∴159 5.3.6 PROCHOT_N Topology and Guidelines 160 5.3.7 THERMTRIP N Topology and Guidelines 161 5.3.8 PWRGOOD Topology and guideline. 5.3.9 RESET_ N Topology and guidelines 162 5.3.10 CPU SMBUs 163 5.3. 11 SViD Topology and guidelines. ....m......................165 167 6. 1 Sandy bridge -eP/eP 4s Processor dIMm Connector layout ..169 6.2 Stackup and referencing Guidelines 170 6.3 DIMM Population Requirements.. 1盖1画 170 6.3.1 General Population Requirements 170 6.3.2 Populating DIMMs Within a Channel 172 6.3.3 Population Requirements for Memory ras Modes 178 6.4 DDR3 Design Topologies and Guidelines. 6.4.1 Three DIMM Slot Per Channel Guidelines (LRDIMM/UDIMM/RDIMM....179 6.4.2 TWo DIMM Slot per channel guidelines ( LRDIMM/ UDIMM/ RDIMM).,…,,,…,…,……,,194 6.4.3 One DIMM Slot Per Channel Guidelines(LRDIMM/UDIMM/RDIMM)....202 6.4.4 Miscellaneous DDR3 Signals .aa“a 210 6.5 DIMM Connector 218 219 7.1 Sandy Bridge-EN Processor DIMM Connector Layout 220 7.2 Stack-Up and referencing guidelines. 221 7.3 DIMM Population Requirements 221 7.3.1 General Population Requirements 221 7.3.2 Populating DIMMs Within a Channel 223 7.3.3 Population Requirements for Memory RAs Modes n226 Reference number: 441694 Revision 1 1 intel 7.4 DDR3 Design Topologies and Guidelines 227 7. 4. 1 Channel Routing restrictions 228 4.2 Strobe Mapping and Clock Groups 228 7.4.3 TWO DIMM Slot Per Channel Guidelines (LRDIMMUDIMM/RDIMM) 229 7.4.4 One DIMM Slot Per Channel Guidelines(LRDIMM/UDIMM/RDIMM) ...... 237 7.4.5 Miscellaneous DDR3 Signals 245 7.5 DIMM Connector 253 255 8. 1 Sandy bridge-EP/EP 4S Processor PCIe Interface Guidelines 255 8.1.1 PCIe Test Points and Probing 259 8.1.2 PCle connectors 259 Sandy Bridge-EP/EP 4s Processor PCle Hot-Plug 260 8. 1.4 Sandy bridge-EP/EP 4S Processor PCIe Termination of Unused pcle ports 260 8.1.5 Sandy bridge-EP/EP 4S Processor PCle PE_VREF_CAP 260 8.1.6 Sandy bridge-EP/EP 4s Processor pCie pe bias and PERBIAS SENSE Signal guidelines 61 8. 1.7 Sandy bridge-EP/EP 4s Processor Direct Media Interface(DMI2).............. 262 One Connector with LAI Transmit,/ Receive routing guidelines.…,丶∴. 8.2 Sandy bridge-EP/EP 4S PCIe Layout Design Guidelines 263 8.2.1 One Connector transmit guidelines 264 8.2.2 One Connector receive guidelines 268 8.2.3 270 8.2.4 TWo Connector Transmit Routing Guidelines ...271 8.2.5 TWo Connector Receive Routing Guidelines 8.2.6 Processor to Down Device Transmit/Receive Routing Guidelines .. .,..... 281 8.2.7 Processor to Down Device with LAI Transmit Routing Guidelines....... 282 8.2.8 Processor to Down Device with LAI Receive Routing Guidelines 284 8.3 sandy Bridge-EN Processor pcle3 Interface Guidelines........ 285 8.3.1 PCle Layout Design Guidelines ∴285 8.3.2 PCIe and dMI Test Points and Probing 287 8.3.3 Connectors ...287 8.3.4 Sandy bridge -EN Processor pcie3 interface 287 8.3.5 Sandy bridge-EN Processor PCle Hot Plug 290 8.3. 6 Sandy bridge-EN Processor PCle, Termination of Unused pcle ports 290 8.3.7 Sandy bridge-EN Processor PCIe PE_VREF CAP 291 8.3. 8 Sandy bridge-EN Processor PCIe PERBIAs and PERBIAS_ SENSE Signal Guidelines..... 291 8.3.9 Sandy bridge- EN Processor direct media interface(DMI2)……… 292 8.3. 10 Sandy bridge-EN Processor PCIe3 Connector Interface guidelines ∴292 8.3. 11 Sandy bridge-EN to a pcie3/PCIe2 down Device∴, ■■ ::::日 316 323 9.1 Patsburg PCh sideband signals 323 9.1.1 CPU CMOS Considerations ..323 9.1.2 RCIN# and A20GATE Design Consideration........ 324 9.1.3 PROCPWRGD Design Consideration……, ,324 9.1.4PML_SYNc,PM_SYNC2 Design Consideration…,…,,…,,,,324 9.1.5 THRMTRIP# Design Consideration.……,…,…,, ,324 9.1.6 Patsburg PCH V_CPU_IO Outputs. 325 9.2 Patsburg pCH- Critical Low Speed signals. ∴325 9.2.1 General design Consideration 326 9.3 Patsburg PCH Interrupt interface 327 9.3.1 PIRQ Example ∴327 9. 4 Patsburg PCh RTC 328 Reference number: 441694, Revision 1.1 5 intel 9.4.1 RTC Layout Considerations........ 330 9.4.2 External Capacitors 330 9.4.3 RTC EXternal Battery Connection..…………331 9. 4. 4 RTC External rtcrst*f circuit 333 9. 4.5 RTC External SrTCRST# Circuit 334 9. 4.6 SUSCLK 334 9.4.7 RTC-Well Input Strap Requirements……………,…,,…,…,,…,334 335 10.1 Patsburg pCh Pci express and dmi interface guidelines 335 10.1.1 Patsburg PCH to Down Device. 338 10.1.2 Patsburg pCh to Connector 342 10.1.3 Patsburg PCH PCle3 and DMI2 Routing 10.1.4 Compensation -ICOMP and RCOMP ,357 10.1.5 PEGO RBIASP/PEGO RBIASN Connection....................357 10.1.6 Requirements for Unrouted Interfaces 359 10.1.7 VCCRBIAS Requirements 0. 1.8 Patsburg PCH PCI E Polarity Inversion 360 10.1.9 Patsburg PCH PCI Express Ports Lane reversal .360 10.1.10 Patsburg PCH to sandy Bridge-EN/EP Processor Connection 361 10.1. 11 Terminating Unused PCI EXpress Ports 361 10.2 Patsburg PCH PCI 361 10.2.1 PCI Routing Summary 362 10.2.2 PCI TAG)Boundary Scan Pins 365 10.3 Patsburg PCH USB 2.0 Interface Guidelines 365 10.3.1 Patsburg PCh USB 2.0 Layout Guidelines 366 10.3.2 Front Panel solutions 371 10.3.3 Patsburg PCH USB Port Power Delivery 373 10.3.4 EMi and Esd Considerations 374 10.3.5 USB Over Current protection ∴378 10.3.6 USBRBIAS/USBRBIAS 10.3.7UsB2.0 Debug port……….……………,………,………,…………381 10.4 SGPIO Interface 1画 ∴381 10.4.1 SATA SGPIO Interface 381 10.42 SAS SGPIO Interface 382 10.5 GPIO Serial Expander bus 384 10.5.1 GPIO Serial Expander Routing guidelines 384 389 11.1 Patsburg PCH Serial ATA (SATA) Interface....... .389 11.1.1 SATA Gen 1 and Gen 2 Routing Requirements and Guidelines ..,...... 390 11.1.2 SATA Gen 3 Routing Requirement and guidelines............... 397 11.1. 3 SATA AC Coupling requirements. 11.1.4 SATA Gen2 Connector Routing Guidelines......... 401 11.1.5 SATA General Purpose signals ............................... 401 11.1.6 SATAICOMPO/SATAICOMPI and sata3RCOMPO/SATA3COMPI Connection. 402 11.1.7 SATALED# Implementation 403 11.1.8 EXternal Serial ATA(eSATA) 403 11. 1.9 SATA TX Setting Selection 407 11.1.10 SATA AHCI 6G and SAs 6G Cable and Connector Requirements......408 11.1.11seria|ATAHostConnectorPlacementConsideratons∴.410 11.2 Serial Attached scsi Interface 413 11.2.1 Serial Attached scsi overview .413 11.2.2 Example of SAs Layout.......... 414 11.2.3 Detailed SAs Routing Guidelines 11.2.4 Topology/Compliance Point Considerations ..420 11.2.5 SAS Connector Requirement 421 6 Reference number: 441694 Revision 1 1 intel 11.2.6 AC Coupling requirements 421 112.7 Reference clock 422 11.2. 8 Terminating Unused sAs interface 426 11.2.9 SAS Transmitter and Receiver: Compliance points. 427 11.2.10 SAS General Purpose I o Signals………,……,…,…,…,…,,427 11.3 Patsburg PCh SPi Interface Guidelines 427 11.3.1 Serial Peripheral Interface(SPI) Overview ∴428 11.3.2 Serial Peripheral Interface(SPI) General routing guidelines ∴429 11.3.3 Single SPi device............... ∴429 11.3.4 Dual SPI Devices -- Topology ............................................................430 11.3.5 Terminating Unused SPI Signals 433 11.3.6 SPI Dual Footprint- So8 and so16 Packages .433 11.3.7 Serial flash∨ endors∴ 434 11.4 Patsburg PCH LPC Interface . 11.4.1 Decoupl up g 435 11.4.2 FWH INIT# Voltage Compatibility 435 11.4.3 FWH VPP Design Guidelines 435 ,437 12.1 Patsburg PCH Power Management Interface 437 12.1.1 SYS RESET# Usage Model 437 2.1.2 SLP A# Usage Model...... 437 12.1.3SLP_S3# Usage Model……,……,…,…,,,……,,,437 12.1.4 SLP_S4# Usage Model.... ∴437 12.1.5 SLP_S5# Usage Model 437 12.1.6 SLP LAN# Usage Model . .....................................................................438 12. 1.7 SLP SUS# Usage Model ,438 12. 1. 8 PWRBtN# Usage Model 438 12.1.9 PLTRST#/ PCIRST# Usage Model.…….……,…………………438 12.1.10 PLTRST# to Processor RsTIN# Design Consideration 439 12.1.11 Power-Well Isolation Control Strap Requirements 40 12,112 RSMRsT# Generation ::““a日:::::a.a ∴4142 12.1.13 PCH PWRoK Generation 442 12114 DRAMPWROK Generation 442 12,1.15 SYS PWROK 443 12.1.16 APWROK 443 12.117 DPWROK 画“ 444 12.1.18 Ps ON Generation 444 12.1.19 Glue Logic device 446 12.1.20 Suspend-To- RAM Sequencing.………………………………………………………446 12.2 Patsburg pCh- SMBus 2.0/SMLink Interface...,.,........ 446 12.21 Monitoring Integrated Sensors Over SMBus……………………448 12.2.2 SMBus Design Considerations. 449 12.2.3 General Design Considerations .............. 449 12.24 Calculating the Physical Segment Pull- Up Resistor…,…,,…450 12.3 Intel@ Management Engine 451 12.3.1 Intel(R Server Platform Services me Firmware 452 el(e Advanced Management Technology(intel AMT) 462 12.3.3 Thermal Signal Guidelines . 12.4 Upgrade rom ∴∴………….469 124.1 Patsburg PCH Upgrade rom SKUs……,,…………469 12.4.2 Upgrade roM Module Overview 470 12.4.3 Upgrade rom implementation Guidelines 471 12.5 PECI (Platform Environmental Control Interface)..... 472 12.5.1 Minimizing PECI Signal Overshoots and Undershoots 476 2.5.2 Romley Platform Board Recommendations to Facilitate PECI Crash Dump Data Collection 477 Reference number: 441694, Revision 1.1 intel 12.6 Patsburg PCH Trusted Platform Module interface ,478 12.6.1 Discrete TPM Design Considerations ““·““.a““ 479 12.6.2 Motherboard placement Consideration 480 481 13. 1 XDP Routing Guidelines .. 13.1.1 General Debug port Overview .481 13.2 Processor XDP Routing guidelines 国画 484 13.2.1 Processor XDP-JTAG Routing Guidelines 484 13.2.2 Processor XDP -Observation Ports Routing guidelines 499 13.2.3 Processor XDP HOoK[7: 0] Pins Routing Guidelines 506 13.2. 4 XDP Present#f 509 13.2.5 I2C /SMBus Routing Guidel 509 13.2.6 POWer ∴509 13.2.7 Processor XDP platform Connection ...m..4.. 509 13.3 BPM Visibility XDP Routing Guidelines... 510 13.3. 1 BPM Visibil ity XDP Platform Connection. 13.4 PCH XDP Routing Guidelines.,.... 51 13. 4.1 PCH XDP-JTAG Routing Guidelines 512 13.4.2 PCH XDP-observation Ports Routing Guidelines.... 515 13.4.3 PCH XDP-System Control Pins Routing Guidelines..... ......................517 13. 4. 4 XDP Present*t 13.4.5 I2C /SMBus Routing Guidelines.....,..I,,.... 519 13.4.6 Power ,519 13.47 PCH XDP Platform connection 519 13.5 XDP Mechanical Specifications . 13.6 Boundary scan Testing 523 13.6. 1 Enabling PCH Boundary scan..... 523 13.6.2 Boundary Scan Test single Scan Chain Considerations...........523 13.7 Support for 3. 3V JTAG Debugger........ 525 137.1 Translation of 3 3v jtag down to pch 1.1V Level525 13.8 DDR3 Memory Logic analyzer probing. ,.,.a 526 13.8.1 High Level Description ∴527 13.8.2 DDR3 Interposer Probe 527 13.8 3 DDR3 VDIMM Probe ……528 138.4 DDR3 Direct probe 528 13.8.5 Probe Placement Configurations 529 13.8.6 Direct probe 530 13.8.7 Mechanical Keep Out Volumes (KOvs) 531 3.8.8 Egress Considerations ∴535 13.8.9 Signal Integrity. 540 13. 8. 10 LA System Power Delivery ∴541 13. 9 Intel QPI Logic Analyzer Probing 541 13.9. 1 High Level Description..........,.......,......... ∴542 13.9.2 Probe Use cases ∴542 13.9.3 Example Use Cases 13.9.4 Probing Requirements for Intel QPI Forwarded Clocks and 544 Reference clocks .546 13.9.5 Keepout Volumes and mechanical interface........ .547 13.9.6 Midbus Probe Footprints.. 561 13.9.7 Midbus trace Shorting 562 13.9.8 Egress Consideration ∴564 13.9.9 Probe Head Cables to Capture Module . 13.9.10 Capture Module Back Side Cables.……,…,…,,,,,,565 13.9.11 Thermal Considerations 566 13.9.12 Platform Clock Requirements 566 13.9.13 Platform Sideband signals 567 8 Reference number: 441694 Revision 1 1 intel 13.9. 14 Interposer Clock Routing . 13.9.15 Midbus system Clock ∴569 13.9.16 Electrical Specifications .571 13.9.17 Probe Power Delivery 13.9.18 Load models ∴572 13.9. 19 Midbus Probe Usage. 573 13.9.20 Sideband routing Topologies….……,……,,…,,,,,,574 13.9.21 Pin Numbering Scheme for Midbus Footprint......... ∴∴576 13.10 PCI Express Gen 3 Logic Analyzer probing..... ∴583 13.10. 1 Configuration Support and specifications. .. 13.10.2 Mechanical Design 585 13. 10.3 Slot Interposer LAI 592 13.10, 4 Reference clock 592 13. 10.5 Electrical Design .....,...... ■111自日1面面 93 13. 10.6 Limitations of Midbus Footprint Pin Assignment Changes 594 13. 10.7 PCI Express* 16 Channel LAI Pin Assignments 13. 10.8 BER of Probing Solution during Speed transition or Link ,. 595 Training periods 111面a11面日日1n直日日1自面1 509 13.10.9 Slot Interposer LAI 09 13.10. 10 Platform Clock Requirements. ..............................................................610 13.10 11 Reference Clock Requirements.. 13.10. 12 RefClk Sourcing for pCle3 Probes on the platform 616 13.10. 13 Electrical Specifications 618 619 14.1 Romley platform Power Distribution Guidelines ∴619 14.2 Baseboard dc-DC Converters 624 14.3 Processor Power Delivery...... 627 14.3.1 PVSA_CPUX(VSA 14.3.2 PVCCPCPUX Output Requirements “..“a...“.aaa 636 14.3.3 PVTT_CPUX VR Requirements 650 14.3.4 PVPLL_CPUX VR Requirements n,654 14.3.5 Romley-EN and Romley-EP 4S CRB Decoupling and Placement.......654 14.3.6 PVDDQXXVR Requirements 1面面面面1111面 655 14.4 DDR 3 Memory DIMMs Power Delivery Guidelines 655 144.1 PVDDQ_ VR Requirements……,,,,,,,,,,,…,656 14.4.2門∨ DDR XX VR VR Requirements.,,,,,, 658 14.4.3 Memory Power Projections. 14.5 Romley platform CRB Voltage Regulator Reference Heatsinks 665 14.6 Romley platform CRBs Thermal Maps 666 14.7 Patsburg PCH- Power Delivery 668 14.7.1 Definitions………… ∴668 14.7.2 Patsburg PCh Power rails..,...,. ∴669 14.7.3 Power Supply ps_ON Consideration ∴670 14.7.4 Patsburg PCH Decoupling /Filter Requirements 671 14.75 Internal VccVRm..,mwwwwwmww..., 675 14.7.6 Power sequencing.,,,.,…,,,,,,,,,,,,…,675 14.7.7 Thermal Design Power 677 679 15.1 Patsburg PCh Lan and82579PHY…………,……,,,……,,… 679 15.2 PHY Overview 680 15.2.1 PHY Interconnects t1n n 680 5.2.2 PCle-Based interface 681 5.2.3 SMBus Interface ∴681 15.2 4 PCIe and smbus modes a:日aa:aa:..a:a:.日a:aa:a:.B日:aaa1:aaBa:.1:: ...... 682 15.2.5 Transitions between PCle and smbus interfaces 682 Reference number: 441694, Revision 1.1 intel 15.3 Platform LAN Design Guidelines 683 15.3. 1 General design Considerations for PHYS 683 15.3.2 NVM for PHY Implementations 685 15.3.3LED. 685 15.3. 4 Exposed Pad*(e-Pad)Design and SMT Assembly Guide ∴686 15.4 Patsburg PCh-SMBus/PCIe LOM Design Guidelines.... ∴691 15.5 SMBus Design Considerations 692 15.6 General Layout Guidelines......,. 693 15.7 Layout Considerations ∴693 15.8 Guidelines for Component placement. 693 15.8.1 PHY Placement Recommendations .694 15.9 MDI Differential-Pair trace routing for lAN Design ∴695 15.10 Signal Trace Geometry .695 15.11 Trace Length and Symmetry……, ■日11面 ∴.697 15.12 Impedance Discontinuities ∴698 15.13 Reducing Circuit Inductance 10010 698 15.14 Signal Isolation....... 698 15.15 Power and ground planes ■量1面 699 15.16 Traces for Decoupling Capacitors . ...,................................................................701 15.17 Ground planes under a magnetics module .701 15. 18 Light emitting diodes .704 15.19 Frequency Control Device Design Considerations 704 15.20 Crystals and Oscillators∴…… ∴.705 15.21 Quartz Crystal 705 15.22 Fixed Crystal Oscillator∴…,…,…,…,…,,…,,…,… 705 15.23 Crystal Selection Parameters 706 15.24 Vibrational mode ∴706 15.25 Nominal Frequency.......... ∴706 15.26 Frequency Tolerance........ 706 15.27 Temperature Stability and Environmental Requirements 706 15.28 Calibration mode 707 15.29 Load Capacitance............... ∴707 15.30 Shunt Capacitance..... 708 5.31 Equivalent Series Resistance......,..,. ∴708 15.32 Drive level 708 15.33 Aging... ::.aaaa:.a:..:a:::aaaaa:a ∴708 15.34 Reference Crystal ∴708 15.34.1 Reference Crystal Selection 708 15.342 Circuit board 709 15.34.3 Temperature Changes 709 15.35 Oscillator Support.……,…,…,…,…,…,…,,…,…,…,…,,…,,,709 15.36 Oscillator Placement and Layout recommendations 710 15.37 Troubleshooting Common Physical Layout Issues............,... 711 15.38 Power Delivery 712 15.39 82579 Power sequencing 713 15.40 Intel Ethernet Controller 10G X540 15.41 Intel( 10 GbE Controller 715 15.42 Intel@R 82580 Quad PCle Network Controller 717 15.43 Intel 82574 GbE Family Network Controller 718 15.44 Intel@ I350 Quad/ Dual GbE 15.45 Intel 82576 Gigabit Ethernet Controller 721 15.46 Intel High Definition audio. 722 15.46.1 Intel@ HD Audio Layout Guidelines ............... 15.46.2 Digital Link Header 725 15.46.3 Intel(R Hd Audio front panel audio control. ............................................727 15.46.4 Intel(R HD Audio Implementation Considerations 732 Reference number: 441694 Revision 1.1

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