Assembly Language Programming Tools for the IA-64 Architecture 1
Assembly Language Programming
Tools for the IA-64 Architecture
Ady Tal, Microprocessor Products Group, Intel Corporation
Vadim Bassin, Microprocessor Products Group, Intel Corporation
Shay Gal-On, Microprocessor Products Group, Intel Corporation
Elena Demikhovsky, Microprocessor Products Group, Intel Corporation
Abstract
The IA-64 architecture, an implementation of Explicitly
Parallel Instruction Computing (EPIC), enables the
compiler to exercise an unprecedented level of control
over the processor. IA-64 architecture features maximize
code parallelism, enhance control over microarchitecture,
permit large and unique register sets, and more. Explicit
control over parallelism adds a new challenge to assembly
writing, since the rules that determine valid instruction
combinations are far from trivial, introducing new
concepts such as bundling and instruction groups.
This paper describes Intel’s IA-64 Assembler and IA-64
assembly assistant tools, which can simplify IA-64
assembly language programming. The descriptions of the
tools are accompanied by examples that use advanced IA-
64 features.
INTRODUCTION
The IA-64 architecture overcomes the performance
limitations of traditional architectures and provides
maximum headroom for future development. Intel’s
innovative 64-bit architecture allows greater instruction-
level parallelism through speculation, predication, large
register files, a register stack, advanced branch
architecture, and more. 64-bit memory addressability
meets the increasingly large memory footprint
requirements of data warehousing, e-Business, and other
high-performance server and workstation applications.
Significant effort in the architectural definition maximizes
IA-64 scalability, performance, and architectural longevity.
In the 64-bit architecture, the processor relies on the
programmers or the compiler to set parallelism boundaries.
Programmers can decide which instructions are executed
in each cycle, taking data dependencies and availability of
microarchitecture resources into account. Assembly can
be the preferred programming language under the
following situations: when learning new computer
architectures in depth; when programming at a low level,
such as that required for BIOS, operating systems, and
device drivers; and when writing performance-sensitive
critical code sections that power math libraries, multimedia
kernels, and database engines.
Intel developed the Assembler and the Assembly
Assistant in order to aid assembly programmers in rapidly
writing efficient IA-64 assembly code, using the assembly
language syntax jointly defined by Intel and Hewlett-
Packard*.
The Intel® IA-64 Assembler is more than an assembly
source code-to-binary translator. It can take care of many
assembly language details such as templates and
bundling; it can also determine parallelism boundaries or
check for those given by assembly programmers. The
assembler can also allocate virtual registers and so enable
assembly programmers to write code with symbolic names,
which are replaced automatically with physical registers.
The Assembly Assistant is an integrated development
tool. It provides a visual guide to some IA-64 architecture
features permitting assembly programmers to comprehend
the workings of the processor. The Assembly Assistant
has three main goals: to introduce the architecture to new
assembly programmers; to make it easier to write assembly
code and use the Assembler; and to help assembly
programmers get maximum performance from their code.
This last task is achieved through static analysis, a drag-
and-drop interface for manual optimization, and through
automatic optimization of code segments.
IA-64 ARCHITECTURE FEATURES FOR
ASSEMBLY PROGRAMMING
The IA-64 architecture incorporates many features that
enable assembly programmers to optimize their code for
efficient, high-sustained performance. To allow greater
instruction-level parallelism, the architecture is based on