Abstract On-chip interconnects are predicted to be a fundamental issue in designing
multi-core chip multiprocessors (CMPs) and system-on-chip (SoC) architectures
with numerous homogeneous and heterogeneous cores and functional blocks.
To mitigate the interconnect crisis, one promising option is network-on-chip (NoC),
where a general purpose on-chip interconnection network replaces the traditional
design-specific global on-chip wiring by using switching fabrics or routers to connect
IP cores or processing elements. Such packet-based communication networks
have been gaining wide acceptance due to their scalability and have been proposed
for future CMPs and SoC design. In this chapter, we study the combination of both
three-dimensional integrated circuits and NoCs, since both are proposed as solutions
to mitigate the interconnect scaling challenges. This chapter will start with a
brief introduction on network-on-chip architecture and then discuss design space
exploration for various network topologies in 3D NoC design, as well as different
techniques on 3D on-chip router design. Finally, it describes a design example of
using 3D NoC with memory stacked on multi-core CMPs.
