4/6/2012 9MV5L
Preliminary Data Sheet
BCM5892/BCM5893
5892_5893-DS07-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 January 20, 2012
System-on-a-Chip
4/6/2012 9MV5L
BROADCOM System-on-a-Chip
January 20, 2012 • 5892_5893-DS07-R Page 2
®
BCM5892/BCM5893 Preliminary Data Sheet
Revision History
Updated: Customer Impact Action Items
Revision: 5892_5893-DS07-R
Date: 01/20/12
Updated:
• Ordering information.
–
Revision: 5892_5893-DS06-R
Date: 12/16/11
Added:
• Section 28: “Synchronous
Peripheral Interface,” on page
978
–
Revision: 5892_5893-DS05-R
Date: 11/23/11
––
Updated: Customer Impact Action Items
• “Voltage Monitor” on page 306
––
• Table 1125: “External Interrupts/
GPIO-B,” on page 1287
––
• Table 1128: “8-Bit SDIO/SPI/
GPIO-E,” on page 1296
––
Added:
• Section : “About This
Document” on page 65
––
• Information under
Table 906: “CNV_DAC_CONFIG,”
on page 976
––
Removed:
• EMI_PVT_COMP - SDRAM pad pvt
Compensation Control Register
table
––
Revision: 5892_5893-DS04-R
Date: 10/18/2010
Note: Page numbers referred are valid only for this revision of the document.
Updated: Customer Impact Action Items
Cover – –
• Table 61: “CFG_UMC_PAD_PARAMS
., Address = 0x0102501C,” on
page 148
––
• Table 62: “CFG_SPI2_PAD_PARAMS,
Address = 0x01025020,” on
page 148
––
• Table 63: “CFG_SDA_PAD_PARAMS.,
Address = 0x01025024,” on
page 149
––
4/6/2012 9MV5L
BROADCOM System-on-a-Chip
January 20, 2012 • 5892_5893-DS07-R Page 3
®
BCM5892/BCM5893 Preliminary Data Sheet
• Table 64: “CFG_URT1_PAD_PARAM
S., Address = 0x01025028,” on
page 149
––
• Table 84: “PMB_CONTROL,” on
page 181
––
• Table 257: “Channel Clear
Register,” on page 284
––
• Table 258: “Channel Clear
Register,” on page 284
––
• Table 259: “Channel Clear
Register,” on page 285
––
• “BBL_Tamper_Src_Enable
Register, Address = 0x0102800B”
on page 324
––
• Table 1006: “UARTCR Register,”
on page 1142
––
• Figure 312: “BCM5892/BCM5893
Ball Map,” on page 1323
––
• “GPD (18) Auxiliary Mapping
Details” on page 1138
––
• Table 1115: “Signals by Ball
Number,” on page 1266
––
• Table 1116: “Signals by Ball
Name,” on page 1272
––
• Section 32: “GPIO,” on page 1086
––
• “Auxiliary Interface Mapping” on
page 1094
––
• “GPD (18) Auxiliary Mapping
Details” on page 1143
––
• Table 1139: “Absolute Maximum
Rating,” on page 1314
––
Revision: 5892_5893-DS03-R
Date: 08/30/2010
Note: Page numbers referred are valid only for this revision of the document.
Updated: Customer Impact Action Items
• Table 50: “Boot Source Options,”
on page 135 (SPI4)
Removed SPI2 and added SPI4
as an available boot source
Confirm correct boot sources on
any new design
• Description for SCFG[5] in “Secure
Keys” on page 263.
Performance difference
depending on selection of
parity or ECC memory
protection
Review internal scratch RAM
usage to determine which type of
memory protection to use
• BBL scratch RAM access time and
power consumption in “Secure
and Scratch BBRAM” on page 300.
BBL scratch RAM is accessed at
8 MHz when the core is powered
resulting in higher current draw
Design review. Always switch
P3P3_VDD supply from battery to
main power supply when the core is
powered to maximize battery life.
Updated: Customer Impact Action Items
4/6/2012 9MV5L
BROADCOM System-on-a-Chip
January 20, 2012 • 5892_5893-DS07-R Page 4
®
BCM5892/BCM5893 Preliminary Data Sheet
• BBL frequency monitor usage in
“Frequency Monitor” on
page 303.
Frequency monitor tampers at
POR or BBL soft reset can be used
to detect presence of BBL clock.
Software review to check for
utilization of this feature to detect
for BBL clock.
• External tamper pin pull values in
“External Tamper Sources” on
page 306
Pulls must be to P3P3_VDD rail Schematic review for pulls to correct
rail and values.
• BBL RTC maximum value in
“BBL_RTC_Time Register, Address
= 0x01028010” on page 324
RTC does not roll over when
reaching max value of
0xFFFFFFFE.
Review of RTC usage and possible
modification of software to handle
rollover.
• BBL RTC initialization using
preload in “BBL_RTC_Div Register,
Address = 0x01028002” on
page 328 and “BBL_Control
Register, Address = 0x01028007”
on page 332
Clarification of RTC initialization. Review RTC software to ensure
correct initialization sequence using
bbl_rtc_preload bit.
• Temperature sensor equations
updated in “BBL_TADC_Value
Register, Address = 0x01028010”
on page 347
Temperature sensor equations
updated for better accuracy.
Software review to check for correct
temperature equations.
• ECC diagram, Figure 156: “ECC
Basic Operation,” on page 805
Clarify use of ECC Last bit usage Review ECC configuration for NAND
• Clarification of
ecc_ignore_add_eight bit on
page 806.
Affects small block NAND ECC
writes
Review usage of this bit if using
small block NAND to ensure correct
operation of ECC writes.
• GPIO behavior during POR and L1
reset. GPIOs are tri-stated during
POR and default pulls are enabled
during L1 reset. (See “Auxiliary
Interface Mapping” on
page 1145.)
Affects GPIO behavior during POR
and L1 reset
Schematic review
• DMU interrupt clear description,
in “DMU Interrupts” on
page 1306, p.1292, 1301
Clarification on how to clear the
DMU interrupt
Review if using the DMU interrupt
• I/O DC Electrical characteristics
updated in “I/O DC Electrical
Characteristics” on page 1403 and
page 1315
Several DC parameters changed Review design to ensure compliance
with specification.
• Current consumption updates in
Table 1200: “Current
Consumption,” on page 1419
Typical and max currents updated
for different rails
Review design to ensure compliance
with specification.
Added: Customer Impact Action Items
• Defined fault check period as tied
to LFSR period
Fault check period defined for
external mesh pins
Confirm configuration of glitch
filtering for any external mesh grid
pins in BBL block.
• External mesh filter configuration
in Table 296: “BBL_AFE_Cfg,” on
page 345.
Configuration bits defined in
BBL_AFE_CFG register
Customer should be aware that
glitch filtering on the external mesh
pins is available.
Updated: Customer Impact Action Items
4/6/2012 9MV5L
BROADCOM System-on-a-Chip
January 20, 2012 • 5892_5893-DS07-R Page 5
®
BCM5892/BCM5893 Preliminary Data Sheet
• Vectored and Non-Vectored
Interrupt flow sequence in
“Vectored Interrupt Flow
Sequence Using AHB” on page 93
and “Nonvectored Interrupt Flow
Sequence Using AHB” on page 94
None Customer reference
• “Daisy-Chain Effect on Interrupt
Priorities” on page 96
Interrupt processing may be
different than expected when
servicing daisy chained interrupt
sources
Review operation and investigate
impact on interrupt processing.
• Table 271: “BBL_LOCK[1:0] Bits,”
on page 317
Change in functionality of secure
memory clearing
Review for correct secure memory
clear operation
• EPHY initialization sequence in
“Initialization Sequence” on
page 637
Definition of EPHY initialization Software review to ensure proper
init of EPHY
• “Overshoot and Undershoot on
Signal Lines” on page 1402
Definition added for Overshoot
and Undershoot
Reference for signaling compliance.
• “I/O Timing Waveforms and
Parameters” on page 1406
Timing spec for LCD, SDIO, I2S,
SPI, SCI, BSC, SRAM, NOR, NAND
and JTAG.
Reference for signaling compliance.
Revision: 5892_5893-DS02-R
Date:10/15/09
Note: Page numbers referred are valid only for the current revision of the document.
Updated: Customer Impact Action Items
• Figure 1: “System Diagram,” on page 6
• “System Interrupt Sources” on page 36
• Table 38: “System Bus Configuration Register Address Map Details,” on page 49
• Table 42: “Open DMA Request Line Assignment,” on page 52 and Table 43: “Secure DMA Channel
Assignment,” on page 53
• “SBI Authentication” on page 71 and “Asymmetric SBI Authentication” on page 72
• “Secure Keys” on page 185
• Table 201: “Register Map (NVM Base Address = 0x01022000),” on page 186
• “OEM Customization Keys” on page 185
• Section 13: “Battery Backed Logic” on page 214
• “RTC Alarm Output” on page 220
• Figure 47: “RTC Alarm Logic,” on page 221
• “External Tamper Mesh Configuration” on page 225
• Table 286: “BBL_Config Register,” on page 249
• Table 293: “BBL_AFE_Cfg,” on page 259
• Table 517: “Register Map Detail,” on page 481
• “Auto-Negotiation Enable” on page 528
• Table 618: “100BASE-X False Carrier Sense Counter (Address 19d, 13h),” on page 539
Updated (Continued): Customer Impact Action Items
Updated: Customer Impact Action Items
