RK3288 GPIO的相关寄存器的介绍和使用

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RK3288 GPIO的相关寄存器的详细介绍和使用
RK3288 TRM gpIo porta eoiN gpio rawintstatuS/ gpio ext portaN Rising Edge gpio intstatusN Detect +- Debounce Falling EdgehC Detect gpio intr flag OR Pol gpio debounceN ActNve-High Detect gpio IntmaskN Active-Low gpio Int level Detect gpio int polarity Fig 49-2 GPIO Interrupt rtL Block Diagram Debounce operation Port a has been configured to include the debounce capability interrupt feature. The external signal can be debounced to remove any spurious glitches that are less than one period of the external debouncing clock When input interrupt signals are debounced using a debounce clock(pclk, the signals must be active for a minimum of two cycles of the debounce clock to guarantee that they are registered Any input pulse widths less than a debounce clock period are bounced a pulse width between one and two debounce clock widths may or may not propagate, depending on phase relationship to the debounce clock. If the input pulse spans two rising edges of the debounce clock it is registered. If it spans only one rising edge, it is not registered Synchronization of Interrupt signals to the System Clock Interrupt signals are internally synchronized to pclk. Synchronization to pclk must occur for edge-detect signals. With level-sensitive interrupts synchronization is optional and under software control (GPIO_LS_SYNC) 49.3.2 Programming Programming Considerations Reading from an unused location or unused bits in a particular register always returns zeros There is no error mechanism in the apb Programming the gPio registers for interrupt capability, edge-sensitive or level-sensitive interrupts, and interrupt polarity should be completed prior to enabling the interrupts on Port a in order to prevent spurious glitches on the interrupt lines to the interrupt controller Writing to the interrupt clear register clears an edge-detected interrupt and has no effect on alevel-sensitive interrupt 9 GPIOs hierarchy in the chip GPIO0 is in PD_PMU subsystem GPIo1v8 are in PD_ALIvE subsystem 49.4 Register Description This section describes the control/status registers of the design Software should read and write these registers using 32-bits accesses. There are 9 GPIOs(GPIOO N GPio8), and each of them has same register group. Therefore, 9 GPIOs register groups have 9 different base FuZhou rockchip Electronics Co, Ltd 1579 RK3288 TRM address 49. 4.1 Registers Summary Reset Name Offset size Description Value GPIO_SWPORTA_DR W 0X00000000 Port a data register GPIO SWPORTA DD 0×0004W|0×00000 Port a data direction register R GPIO INTEN 0×0030W/0×00000 nterrupt enable register GPIO_INTMASK0x0034 Interrupt mask register GPIO INTTYPE LEV 0x0038W0x00000000 Interrupt level register GPIO_INT_POLARITY 0X003cW Interrupt polarity register GPIO_INT_STATUS0x0040woxoo0ooooo Interrupt status of port A GPIO INT RAWSTAT 0x0044W0X00000000 Raw Interrupt status of port Al US GPIO DEBOUNCE 0x00000000 Debounce enable register GPIO_PORTA_EOI 0x004cW 0X00000000 Port a clear interrupt register GPIO_EXT_PORTA0x0050Woxo00oo0ooport A external port register Level sensitive GPIO LS SYNC 0×0060W0×0000000 ynchronization enab|e register Notes: Size: B-Byte(8 bits)access, HW- Half WORD (16 bits)access, W-WORD (32 bits access 49.,4.2 Detail Register Description GPIO SWPORTA DR Address: Operational Base offset(0X0000) Port a data register Bit Attr Reset Value Description gpio swporta dr values written to this register are output on 31:0RW 0x00000000the I/ O signals for Port A if the corresponding data direction bits for port a are set to output mode. The value read back is equal to the last value written to this register GPIO SWPORTA DDR Address: Operational Base +offset(0x0004) Port a data direction register Bit Attr Reset Value Description FuZhou rockchip Electronics Co, Ltd 1580 RK3288 TRM Bit Attr Reset Value Description gpIo swporta ddr Values written to this register independently control the direction of the corresponding data 31:0RW 0x00000000 bit in port a 1b0: Input(default) 1bl: Output GP工 O INTEN Address: Operational Base offset(0x0030) Interrupt enable register Bit Attr Reset Value Description gpio_int_en Allows each bit of port a to be configured for interrupts.Whenever a 1 is written to a bit of this register, it configures the corresponding bit on Port a to become an interrupt otherwise, port A operates as a normal GPIo 31:0|RW 0×00000000| signal. Interrupts are disabled on the corresponding bits of port a if the corresponding data direction register is set to Output. 1'b0: Configure port a bit as normal gPio ignal (default) 1b1: Configure Port a bit as interrupt GPo工 NTMASK Address: Operational Base offset(0X0034) Interrupt mask register Bit Attr Reset Value Description gpIo int mask Controls whether an interrupt on port a can create an interrupt for the interrupt controller by not masking it. Whenever a l is written to a 31:0 RW 0x00000000 bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through 1b0: Interrupt bits are unmasked(default) 1bl: Mask interrupt GP工 O INTTYPE LEVEL Address: Operational Base offset (0x0038 Interrupt level register Bit Attr Reset Value Description FuZhou rockchip Electronics Co, Ltd 1581 RK3288 TRM Bit Attr Reset Value Description gpio inttype_ leve Controls the type of interrupt that can occur 31:0RW 0×00000000 on port a 1b0: Level-sensitive(default) 1b1: Edge-sensitive GP工 O INT POLARITY Address: Operational Base offset(0X003c) Interrupt polarity register Bit Attr Reset Value Description gpio _int_polarity Controls the polarity of edge or level 31:0RW 0x00000000 sensitivity that can occur on input of Port A 1b0: Active-low(default) 1 b1: Active-high GPIO INT STATUS Address: Operational Base offset(0x0040) Interrupt status of port A Bit Attr Reset Value Description 31:0Ro 0X00000000 gpIo_Int-status Interrupt status of port A GPIO INT RAWSTATUS Address: Operational Base offset (0X0044) Raw Interrupt status of port A Bit Attr Reset Value Description gpio_int_rawstatus 31:0 RO 0x00000000 Raw interrupt of status of Port A(premasking bits GPIO DEBOUNCE Address: Operational Base offset(0x0048) Debounce enable register Bit Attr Reset Value Description gpio debounce Controls whether an external signal that is the source of an interrupt needs to be debounced to remove any spurious glitches. Writing a l to 31:0|RW 0×00000000 a bit in this register enables the debouncing circuitry. A signal must be valid for two periods of an external clock before it is internally processed 1b0: No debounce (default) 1 b1: Enable debounce FuZhou rockchip Electronics Co, Ltd 1582 RK3288 TRM GPIO PORTA EO工 Address: Operational Base offset(0X004c Port a clear interrupt register Bit Attr Reset Value Description gpio -porta_eol Controls the clearing of edge type interrupts from port a when a 1 is written into a Corresponding bit of this register the 31:0Wo 0×00000000 interrupt is cleared all interrupts are cleared when Port a is not configured for interrupts. 1b0:No interrupt clear(default) 1b1: Clear interrupt GPIO EXT PORTA Address: Operational Base offset(0x0050) Port a external port register Bit Attr Reset Value Description gpio_ext_porta When Port a is configured as Input, then reading this location reads the values on the 31:0RO 0x00000000 signal. When the data direction of Port A is set as Output reading this location reads the data register for Port A GPIO LS SYNC Address: Operational Base offset(0X0060) Level_ sensitive synchronization enable register Bit Attr Reset Value Description 31:1Ro 0x0 reserved gpio_Is_sync Writing a 1 to this register results in all RW/0×0 level-sensitive interrupts being synchronized to pclk intr 1b0: No synchronization to pclk_intr(default 1b1: Synchronize to pclk intr 49iNterface description Table 49-1 GPIo interface description Module Pin Dir Pad Name IOMUX Setting GPIOO Interface GRF_GPIOOA_IOMUX[15: 0 gpio_porta[7: 0] I/0 GPIO0-_A[7: 0 =16h0000 gpio0_porta[15: 8]I/0 GPIO0_B[7: 0 GRF_GPIOOB_IOMUX[15: 0] =167h0000 gpio_porta[23: 16] I/0 GP100_C[7: 0]GRF_GPIOOC_IOMUX[15: 0] FuZhou Rockchip Electronics Co, Ltd 1583 RK3288 TRM =167h0000 GRF GPIOOD IOMUX[15: 0] gpio_porta [ 31: 24] I/0 GPIO0_D[7: 0] =16h0000 GPIO1 Interface GRF GPIO1A_IOMUX[15: 0] gpio1_porta[7: 0] Iy0 GPIO1_A[7: 0] =16h0000 gpio1_porta[ 15: 8] I/0 GPIO1_B[7: 0 GRF_ GPIO1B_ IOMUX[15: 0] 167h0000 gpio1_porta[23: 16] I/0 GPIO1_C[7: 0 GRF_ GPIo1C_IOMUX[15: 0] 167h0000 GRF_ GPIO1D_IOMUX[15: 0] gpio1_porta[31: 24] I/0 GPIO1_D[7: 0 16h0000 GPIO2Interface gpio2_porta[7: 0] I/0 GPIO2_A[7: 0 GRF_GPIO2A_IOMUX[15: 0] =16h0000 gpio2_porta[15: 8] I/0 GPIO2_B[7: 0 GRF_GPIO2B_IOMUX[15: 0] =16h0000 gpio2_porta[23: 16] I/0 GPIO2_C[7: 0] GRF_ GPIO2C_IOMUX[15: 0] =16h0000 GRF_GPIO2D_IOMUXL15: 0 gpio_porta[ 31: 24] I/0 GPIO2_D[7: 0] 167h0000 GPIO3 Interface gpio_porta[7: 0] I/O GPIO3_A[7: 0 GRF_GPIO3AIOMUX[15: 0] =16h0000 gpio 3_porta[ 15: 8]I/O GPIO3_B[7: 0 GRF_GPIO3B_IOMUX[15: 0] =16h0000 gpio3_porta[ 23: 16]I/0 GPIO3_C[7: 0 GRF_GPIO3C_IOMUX[15: 0] =16h0000 gpio_porta[31: 24]I/0 GPI03-_D[7: 01 GRF_GPIO3D_IOMUX[15: 01 =16h0000 49.6 Application Notes Steps to set GPIO's direction Write GPIo SWPORT_DDRix] as 1 to set this gpio as output direction and Write GPIO_ SWPORT_ DDR[X] as0 to set this gpio as input direction Default gPIos direction is input direction Steps to set GPIO's level o Write GPIo SWPORT_dDRix as 1 to set this gpio as output direction o Write GPIo SWPORT DRiX] as v to set this GPIos value Steps to get GPIOs level Write GPIO- SWPORT_ DDRIX] aso to set this gpio as input direction Read from GPIo_EXT_PORT[xIto get GPIOs value Steps to set GPIo as interrupt source o Write GPIO SWPORT_DDR[x] as 0 to set this gpio as input direction FuZhou Rockchip Electronics Co, Ltd 1584 RK3288 TRM Write GPIo_INTTYPE_LEVELlX] as v1 and write GPIo_ INT POLaRITY[X as v2 to set interrupt type o Write GPIO_INTEN[X] as 1 to enable GPIO's interrupt Note: Please switch imux to gPio mode first FuZhou rockchip Electronics Co, Ltd 1585

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