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### 使用 TMS320C6747/C6745/C6743 Bootloader 的关键知识点 #### 引言本应用报告详细介绍了如何利用 TMS370C6747/C6745/C6743 处理器中的 Bootloader ROM 映像来支持多种启动机制。报告由 Urmil Parikh 和 Joseph Coombs 编写，发布于2012年6月，并提供了关于 Application Image Script (AIS) 启动过程、AISgen 工具用于生成启动脚本、从外部主机设备启动设备的协议、通过 UART Boot Host GUI 从 PC 主机启动设备等主题的深入探讨。此外，报告还列出了 Bootloader 的限制、默认设置以及假设条件。 #### 启动模式 TMS320C6747/C6745/C6743 Bootloader 支持多种启动模式，包括 AIS 启动和其他非 AIS 启动模式。这些模式允许用户根据不同的应用场景灵活地选择最合适的启动方式。 #### 非 AIS 启动模式非 AIS 启动模式通常是指那些不依赖于 Application Image Script 文件的启动方法。这类启动模式包括但不限于直接从 NOR/NAND Flash 或其他外部存储器启动。这些模式对于那些不需要复杂脚本处理的应用场景非常有用。 #### Application Image Script (AIS) 启动 AIS 启动是 TMS320C6747/C6745/C6743 Bootloader 的一个重要特性，它允许用户通过定义一系列命令来指导 Bootloader 如何加载和执行应用程序。AIS 文件是一种二进制格式文件，其中包含了 Bootloader 执行的一系列操作指令。 - **结构**: AIS 文件由多个命令组成，每个命令都有特定的功能，如 Section Load 命令用于从外部存储器加载数据段到内部存储器，Section Fill 命令用于填充内存区域，Enable/Disable/Validate CRC 命令用于处理 CRC 校验，Start-Over 命令用于重启 AIS 执行等。 - **流程**: Bootloader 会按照 AIS 文件中定义的顺序逐条执行命令。这为用户提供了极大的灵活性，可以根据具体的应用需求定制启动过程。 #### AISgen: 用于生成 AIS 图像的工具 AISgen 是一个辅助工具，可以帮助用户轻松地生成 AIS 文件。该工具具有图形用户界面 (GUI)，用户可以直观地指定启动过程中的各个步骤，如加载数据段的位置、CRC 设置等。AISgen 使得创建复杂的启动脚本变得更加简单。 - **功能**: AISgen 支持创建各种 AIS 命令，包括但不限于 Section Load、Section Fill、CRC 相关命令等。 - **GUI**: AISgen 提供了一个易于使用的界面，用户可以通过拖放等方式快速构建 AIS 文件。 #### Master Boot - 从 Slave 存储设备启动在 Master Boot 模式下，设备作为 Slave 从外部存储器启动。这种模式适用于需要从外部存储器读取数据或代码的应用场景。Bootloader 会从指定的地址开始读取数据，并将其加载到内部存储器中执行。 #### Slave Boot - 从外部 Master 主机启动与 Master Boot 类似，但在 Slave Boot 模式下，设备作为一个 Slave 设备接收来自外部 Master 主机的数据。这种模式通常用于调试和开发过程中，通过外部主机控制启动过程。 #### UART Boot Host - 使用 PC 作为 UART Boot 主机 UART Boot Host 是一种通过 UART 接口从 PC 主机启动设备的方法。这种方式通常用于开发阶段，便于调试和测试。用户可以通过专用的软件工具（例如 UART Boot Host GUI）来控制启动过程。 #### 启动要求、约束及默认设置报告还详细讨论了 Bootloader 在启动过程中的一些要求、约束和默认设置。这些信息对于理解 Bootloader 的行为至关重要。 - **要求**: 报告列出了启动过程中需要满足的各种硬件和软件条件。 - **约束**: 报告指出了 Bootloader 在执行过程中可能遇到的限制。 - **默认设置**: 报告解释了 Bootloader 在没有明确配置的情况下将采用哪些默认值。 #### 附录报告还包括了几个附录，涵盖了启动模式选择表、支持的 NAND 设备详情、CRC 计算算法、预定义的 ROM 函数详情以及 ROM 修订历史等内容。这些补充材料为用户提供了更全面的理解，有助于在实际应用中正确使用 Bootloader。 TMS320C6747/C6745/C6743 Bootloader 提供了丰富的功能和高度的灵活性，能够满足不同类型的应用需求。通过对本应用报告的学习，开发者可以更好地掌握如何利用 Bootloader 来优化其产品的启动过程。

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Application Report

SPRABB1C–June 2012

Using the TMS320C6747/45/43 Bootloader

Urmil Parikh and Joseph Coombs........................................................................................................

ABSTRACT

This application report describes various boot mechanisms supported by the C6747/45/43 bootloader

read-only memory (ROM) image. Topics covered include the Application Image Script (AIS) boot process,

an AISgen tool used to generate boot scripts, protocol for booting the device from an external master

device, a UART Boot Host GUI for booting the device from a host PC, and any limitations, default settings,

and assumptions made by the bootloader.

Project collateral discussed in this application report can be downloaded from the following URL:

http://www-s.ti.com/sc/techlit/sprabb1.zip.

Contents

1 Introduction .................................................................................................................. 2

2 Boot Modes .................................................................................................................. 3

3 Non-AIS Boot Modes ....................................................................................................... 3

4 Application Image Script (AIS) Boot ...................................................................................... 5

5 AISgen: Tool to Generate Boot Script (AIS image) ................................................................... 11

6 Master Boot – Booting From a Slave Memory Device ................................................................ 17

7 Slave Boot – Booting From an External Master Host ................................................................. 18

8 UART Boot Host - Using Your PC as a UART Boot Master ......................................................... 22

9 Boot Requirements, Constraints and Default Settings ............................................................... 24

Appendix A Boot Mode Selection Table ..................................................................................... 27

Appendix B Details of Supported NAND Devices ........................................................................... 28

Appendix C CRC Computation Algorithm .................................................................................... 30

Appendix D Details of Pre-Defined ROM Functions ........................................................................ 31

Appendix E ROM Revision History ........................................................................................... 36

List of Figures

1 NOR Boot Configuration Word ............................................................................................ 3

2 Structure of Secondary Bootloader for NOR Boot...................................................................... 4

3 Placement of AIS for NOR Boot .......................................................................................... 4

4 Structure of AIS ............................................................................................................. 5

5 Structure of an AIS Command ........................................................................................... 5

6 Section Load Command ................................................................................................... 6

7 Section Fill Command ...................................................................................................... 6

8 Enable CRC Command .................................................................................................... 6

9 Disable CRC Command.................................................................................................... 7

10 Validate CRC Command................................................................................................... 7

11 Handling CRC Error ........................................................................................................ 7

12 Validate CRC Flow for Slave Mode ...................................................................................... 7

13 Start-Over Command....................................................................................................... 8

14 Jump and Close Command................................................................................................ 8

15 Jump Command............................................................................................................. 8

16 Sequential Read Enable Command ...................................................................................... 9

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Introduction

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17 Compressed Section Load Command ................................................................................... 9

18 Function Execute Command .............................................................................................. 9

19 Boot Table Command..................................................................................................... 10

20 Type Word for Boot Table Opcode...................................................................................... 10

21 AISgen Main Window ..................................................................................................... 12

22 Structure of NAND Page and Spare Bytes............................................................................. 18

23 Flowchart: Start-Word Synchronization................................................................................. 19

24 Flowchart: Ping Op-Code Synchronization............................................................................. 21

25 Flowchart: Op-Code Synchronization................................................................................... 22

26 UART Boot Host utility .................................................................................................... 23

27 I2C SDA Signal Diagram for I2C EEPROM Boot .................................................................... 25

28 SPI Mode for Communication............................................................................................ 25

29 SPI Signal Diagram for SPI EEPROM Boot ........................................................................... 26

30 PLL Configuration Register .............................................................................................. 31

31 SPI Master Register....................................................................................................... 32

32 I2C Master Register....................................................................................................... 32

33 I2C Master Register....................................................................................................... 33

List of Tables

1 NOR Boot Configuration Word Field Descriptions...................................................................... 3

2 Type Word for Boot Table Opcode Field Descriptions ............................................................... 10

3 Values of Non-User Configurable PLL Dividers ....................................................................... 14

4 Default Clock Configurations for Various Boot Modes ............................................................... 24

5 Default PLL Configuration in I2C1 Slave-Boot Mode ................................................................. 25

6 Boot Mode Selection ...................................................................................................... 27

7 List of Supported NAND Devices........................................................................................ 28

8 Expected Contents of Fourth ID Byte for NAND Devices Listed in With Sizes Greater Than 128 MB ........ 29

9 List of Pre-Defined ROM Functions..................................................................................... 31

10 PLL Configuration Register Field Descriptions ........................................................................ 31

11 SPI Master Register Field Descriptions ................................................................................ 32

12 I2C Master Register Field Descriptions................................................................................. 32

13 I2C Master Register Field Descriptions................................................................................. 33

14 Power and Sleep Configuration (PSC) Register Field Descriptions ................................................ 34

15 Pinmux Configuration Register Field Descriptions .................................................................... 35

1 Introduction

The C6747/45/43 bootloader resides in the ROM of the device. This document describes the boot protocol

used by the bootloader, discusses tools required to generate boot script, and talks about limitations and

assumptions for the bootloader.

The C6747/45/43 bootloader has undergone multiple revisions. To check the version of your device,

perform the following steps.

1. Connect to the device in the Code Composer Studio™ software.

2. Select View → Memory.

3. Enter the address of the beginning of the ROM, 0x11700000, at the top of the memory window.

4. Select Character mode at the bottom.

Code Composer Studio is a trademark of Texas Instruments.

Windows, Microsoft are registered trademarks of Microsoft Corporation in the United States and/or other countries.

All other trademarks are the property of their respective owners.

Using the TMS320C6747/45/43 Bootloader SPRABB1C–June 2012

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Boot Modes

The text d800k005 should appear in the memory window at offset 0x08. For earlier ROM revisions, the

text could also appear as d800k003, d800k001. It’s important to know your ROM revision when generating

boot images. If you don’t see either of these values in the memory window, this document is not

applicable to your device.

2 Boot Modes

The bootloader supports booting from various memory devices (master mode) as well as from an external

master (slave mode). A complete list of the supported boot modes and the configuration of the boot pins

to select each one of them can be found in Appendix A.

All boot modes, except the host port interface (HPI) and two out of the three NOR-boot modes, make use

of the AIS for boot purpose. AIS is a Texas Instruments, Inc. proprietary boot script format widely used in

TI devices. All boot modes supporting AIS present a unified interface to you. AIS and AISgen, the tool

used to generate AIS, will be discussed in detail later in this document.

There are few boot modes that do not make use of AIS and have a special boot interface. For instance,

• The HPI boot method requires the HPI host to load the application image to the device memory and

does not use AIS.

• There are three methods to boot from a NOR Flash, only one of which uses AIS.

Each of these will be discussed later in the document.

3 Non-AIS Boot Modes

3.1 NOR Boot

NOR (or parallel Flash) boot happens from a NOR Flash device connected to the external memory

interface (EMIFA) peripheral on EMA_CS[2]. For this boot mode, the bootloader configures EMIFA for 8-

bit access and reads the first word from the NOR Flash. This first word indicates if the NOR Flash should

be accessed in 16-bit or 8-bit mode, as well as which boot method to be used. This word is interpreted as

shown in Figure 1

The NOR boot configuration word register is shown in Figure 1 and described in Table 1.

Figure 1. NOR Boot Configuration Word

31 12 11 8

Reserved COPY

7 6 5 4 3 1 0

Reserved METHOD Reserved ACCESS

Table 1. NOR Boot Configuration Word Field Descriptions

Bit Field Value Description

31-12 Reserved 0 Reserved

11-8 COPY Length of data to copy from the base of the NOR Flash to the base of the digital signal processor

(DSP) L2 RAM. This value is used only for the Legacy NOR boot method.

0x00 1 KB

0x01 2 KB

0x0E 15 KB

0x0F 16 KB

7-6 Reserved 0 Reserved

5-4 METHOD Boot method

0x0 Legacy NOR boot

0x1 Direct NOR boot

0x2 AIS NOR boot

3-1 Reserved 0 Reserved

SPRABB1C–June 2012 Using the TMS320C6747/45/43 Bootloader

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ConfigurationWord

AIS

ConfigurationWord

Secondary

BootLoader

Non-AIS Boot Modes

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Table 1. NOR Boot Configuration Word Field Descriptions (continued)

Bit Field Value Description

0 ACCESS EMIFA access mode

0x0 8-bit access

0x1 16-bit access

If ACCESS == 0x1, bootloader reconfigures EMIFA for 16-bit access before using specified boot

METHOD to boot from NOR. The default configuration of the bootloader is for an 8-bit access.

With a total of 15 address lines (EMA_A[12:0] and EMA_BA[1:0]) of EMIFA, only 32 KB of NOR Flash can

be accessed by the bootloader. If boot image is longer than this, a secondary bootloader is required that

can access more data from NOR Flash by managing higher address lines of NOR Flash using general-

purpose input/output (GPIO) pins or some other mechanism.

3.1.1 Legacy NOR Boot

When METHOD==0x0, the Legacy NOR boot option will be executed. For Legacy NOR boot, the

bootloader copies a block of data, whose size is indicated by the COPY field, from the start of NOR Flash

(address 0x60000000) to the start of DSP L2 RAM (0x11800000). This block of data should hold a

secondary bootloader, as shown in Figure 2.

Figure 2. Structure of Secondary Bootloader for NOR Boot

After copying the required data to DSP L2 RAM, the bootloader transfers control to the secondary

bootloader by branching to address 0x11800004.

3.1.2 Direct NOR Boot

When METHOD==0x1, the Direct NOR boot option will be executed. For Direct NOR boot, the bootloader

transfers control directly to the secondary bootloader present in NOR Flash by branching to address

0x60000004. The secondary bootloader is directly executed from there.

3.1.3 AIS NOR Boot

When METHOD==0x2, the AIS NOR boot option will be executed. When booting with this method, the

bootloader expects the AIS image to start from address 0x60000004, which is mapped to NOR Flash.

Figure 3. Placement of AIS for NOR Boot

Using the TMS320C6747/45/43 Bootloader SPRABB1C–June 2012

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Opcode

Argument

...

Data

...

MagicWord

Command

...

J&CCommand

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Application Image Script (AIS) Boot

The AIS boot method is described in detail later in this document.

3.2 Host Port Interface (HPI) Boot

HPI boot happens from the HPI0 peripheral in 16-bit mode. The boot sequence to boot from HPI is listed

below:

• Bootloader interrupts the host by setting the HINT bit, in the HPIC register, to inform that it is ready and

that the host can start loading the application image to device memory.

• Host acknowledges this interrupt by clearing the HINT bit.

• Host loads the application image to device memory and writes application entry point to location

0x11800000 in device memory.

• Host interrupts bootloader by setting DSPINT bit in HPIC register to inform that loading of application

image is complete.

• Bootloader acknowledges host by clearing DSPINT bit.

• Bootloader reads application entry point (written by host) from address 0x11800000 and branches to it.

4 Application Image Script (AIS) Boot

AIS is a format of storing the boot image. Apart from the HPI and two NOR-boot modes described above,

all boot modes supported by the C6747/45/43 bootloader use AIS for boot purposes.

AIS is a binary language, accessed in terms of 32-bit (4-byte) words in little endian format. AIS starts with

a magic word (0x41504954) and contains a series of AIS commands, which are executed by the

bootloader in sequential manner. The Jump & Close (J&C) command marks the end of AIS.

Figure 4. Structure of AIS

Each AIS command consists of an opcode, optionally followed by one or more arguments, followed by

optional data.

Figure 5. Structure of an AIS Command

The opcode and its arguments are each one word (4 bytes) wide. If the length of data is not a multiple of 4

bytes, it is padded with zeros to make it so.

Knowledge of AIS commands is not required to use the bootloader, but will be discussed in the following

sub-sections for completeness. You can skip to the next section if knowledge of AIS commands is not

desired.

SPRABB1C–June 2012 Using the TMS320C6747/45/43 Bootloader

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