CMOS Circuit Design,Layout,and simulation.pdf

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《CMOS集成电路设计手册》讨论了CMOS电路设计的工艺、设计流程、EDA工具手段以及数字、模拟集成电路设计,并给出了一些相关设计实例,内容介绍由浅入深。该著作涵盖了从模型到器件,从电路到系统的全面内容,是一本权威、综合的CMOS电路设计的工具书及参考书。
Brief contents Chapter 1 Introduction to CMOS Design Chapter 2 The Well 31 Chapter 3 The Metal Layers 59 Chapter 4 The Active and Poly Layers 83 Chapter 5 Resistors, Capacitors, MOSFETS 105 Chapter 6 MoSFET Operation 131 Chapter 7 CMOS Fabrication by Jeff Jessing 161 Chapter 8 Electrical Noise: An Overview 213 Chapter 9 Models for Analog Design 269 Chapter 10 Models for Digital Design 311 Chapter 11 The Inverter 331 Chapter 12 Static Logic Gates 353 Chapter 13 Clocked Circuits 375 Chapter 14 Dynamic Logic Gates 397 Chapter 15 VLsI Layout Examples 411 Chapter 16 Memory Circuits 433 Chapter17 Sensing Using△Σ Modulation 483 Chapter 18 Special Purpose CMOS Circuits 523 Chapter 19 Digital Phase-Locked Loops 551 Chapter 20 Current Mirrors 613 Chapter 21 Amplifiers 657 Chapter 22 Differential Amplifiers 711 Chapter 23 Voltage References 745 Chapter 24 Operational Amplifiers F 773 Chapter 25 Dynamic Analog Circuits 829 Chapter 26 Operational Amplifiers ll 863 Chapter 27 Nonlinear Analog Circuits 909 Chapter 28 Data Converter Fundamentals by Harry LI 931 Chapter 29 Data Converter Architectures by Harry Li 965 Chapter 30 Implementing Data Converters 1023 Chapter 31 Feedback Amplifiers with Harry Li 1099 Contents Preface XXXI Chapter 1 Introduction to CMOS Design 1.1 The CMOs IC Design Process 1.1.1 Fabrication Layout and cross Sectional views 1.2 CMOS Background 6 The CMOS Acronym 6 CMOS Inverter The First CMOS Circuits Analog Design in CMOS 1.3 An Introduction to sPice 8 Generating a Netlist File 8 Operating Point 9 Transfer Function Analysis 10 The Voltage-Controlled Voltage Source An ldeal Op-Am 12 The Subcircuit 13 DC Analysi 13 Plotting IV Curves 14 Dual Loop dc analysis Transient Analysis 15 The sIN Source 16 An RC Circuit Example Another RC Circuit EXample AC Analysis Decades and octaves Decibels 20 Contents Pulse statement 21 Finite Pulse rise time 21 Step Response 22 Delay and rise time in RC Circuits 22 Piece-Wise Linear(PWL) Source 23 Simulating Switches 24 Initial Conditions on a capacitor 24 nitial Conditions in an Inductor 25 Q of an LC Tank 25 Frequency Response of an Ideal Integrator 26 Unity-Gain Frequency 26 Time-Domain Behavior of the Integrator 27 Convergence 28 Some Common Mistakes and Helpful Techniques 29 Chapter 2 The Well 31 The Substrate(The Unprocessed Wafer) 31 A Parasitic Diode 31 Using the N-well as a Resistor 32 2.1 Patterning 32 2.1.1 Patterning the n-well 35 2.2 Laying Out the N-well 2.2. 1 Design Rules for the N-well 36 2.3 Resistance Calculation Layout of corners 38 2.3.1 The N-well Resistor 38 2.4 The N-well/Substrate Diode 39 2. 4. 1 a Brief Introduction to Pn Junction Physics 39 Carrier Concentrations 40 Fermi Energy Level 42 2. 4.2 Depletion Layer Capacitance 43 2. 4. 3 Storage or Diffusion Capacitance 45 2.4.4 SPICE Modeling 47 2.5 The RC delay through the N-well RC Circuit Review Distributed RC Delay 50 Distributed rc rise time 52 2.6 Twin Well Processes 52 Contents Design Rules for the Well 53 SEM Views of Wells 55 Chapter 3 The Metal Layers 59 3.1 The Bonding Pad 59 3.1. 1 Laying Out the Pad I 60 Capacitance of Metal-to-Substrate 60 assivation 62 An Important note 62 3.2 Design and layout using the metal Layers ,63 3.2. 1 Metall and via1 63 An Example Layout 63 3.2.2 Parasitics Associated with the Metal Layers 64 Intrinsic Propagation Delay 65 3.2.3 Current-Carrying Limitations 68 3.2. 4 Design Rules for the metal Layers 69 Layout of Two shapes or a single Shape 69 a Layout Trick for the metal layers 69 3.2.5 Contact Resistance 70 3. 3 Crosstalk and ground bounce 71 3. 3. 1 Crosstalk 71 3.3.2 Ground Bounce 72 DC Problems 72 AC Problems 72 A Final Comment 74 3.4 Layout Examples 75 3.4.1 Laying Out the Pad ll 75 3.4.2 Laying Out Metal Test Structures 78 SEM View of Metal Chapter 4 The Active and Poly Layers 83 4. 1 Layout Using the Active and Poly Layers 83 The active Layer 83 The P-and N-select Layers 84 The Poly Layer 86 Self-Aligned Gate 86 The Poly Wire 88 Silicide Block 89 4.1.1 Process Flow 89 Contents Damascene Process steps 90 4.2 Connecting Wires to Poly and Active 92 Connecting the P-Substrate to Ground 93 Layout of an n-well resistor 94 Layout of an nmos device 95 Layout of a PMos Device 96 A Comment Concerning MOSFET Symbols 96 Standard Cell Frame 97 Design Rules 98 4.3 Electrostatic Discharge(ESD)Protection 100 Layout of the Diodes 100 Chapter 5 Resistors, Capacitors, MOSFETS 105 5. 1 Resistors 105 Temperature Coefficient(Temp Co 105 Polarity of the Temp Co 106 Voltage Coefficient 107 Using Unit Elements 109 Guard rin 110 Interdigitated layout 110 Common-Centroid Layout 111 Dummy Elements 113 5.2 Capacitors 113 Layout of the Poly-Poly Capacitor 114 Parasitics 115 Temperature Coefficient(Temp Co) 116 Voltage coefficient 116 5. 3 MOSFETs 116 Lateral diffusion 116 Oxide Encroachment 116 Source/Drain Depletion Capacitance 117 Source/Drain Parasitic Resistance 118 Layout of Long- Length MOSFETS 120 Layout of large-Width MOSFETs 121 A Qualitative Description of MOSFET Capacitances 123 5. 4 Layout Examples 125 Metal Capacitors 125 Polysilicon Resistors 127 ontents Chapter 6 MOSFET Operation 131 6. 1 MOSFET Capacitance overview/Review 132 Case I: Accumulation 132 Case lI: Depletion 133 Case l: Strong Inversion 133 Summary 135 6.2 The Threshold Voltage 135 Contact Potentials 137 Threshold Voltage Adjust 140 6.3 IV Characteristics of MOSFETs 140 6.3.1 MOSFET Operation in the Triode region 141 6.3.2 The Saturation Region 143 Cgs Calculation in the Saturation Region 145 6. 4 SPICE Modeling of the MOSFET 145 Model parameters related to v 146 Long-Channel MOSFET Models 146 Model parameters related to the drain current 146 SPICE Modeling of the Source and drain Implants 147 Summary 147 6. 4.1 Some sPicE Simulation Examples 148 Threshold voltage and body Effect 148 6.4.2 The Subthreshold current 149 6.5 Short-Channel MOSFETs 151 Hot carriers 151 Lightly Doped Drain(LDD) 15 6.5.1 MOSFET Scaling 152 6.5.2 Short-Channel Effects 153 Negative Bias Temperature Instability(NBti 153 Oxide Breakdown 154 Drain-Induced Barrier Lowering 154 Gate-Induced Drain Leakage 154 Gate Tunnel Current 154 6.5.3 SPICE Models for our short-Channel CMos 154 Process BSIM4 Model Listing(NMOS 154 BSIM4 Model Listing(PMOS) 156 Simulation Results 157 Content: Chapter 7 CMOS Fabrication by Jeff Jessing 161 7.1 CMOS Unit Processes 161 7.1. 1 Wafer Manufacture 161 Metallurgical Grade Silicon(MGS) 162 Electronic Grade Silicon(EGs 162 Czochralski (Cz) Growth and Wafer Formation 162 7.1.2 Thermal Oxidation 163 7.1.3 Doping Processes 165 lon Implantation 165 Solid state Diffusion 166 7.1. 4 Photolithography 167 Resolution 168 Depth of Focus 168 Aligning Masks 70 7.1.5 Thin Film removal 170 Thin Film etching 170 Wet Etching 171 Dry Etching 71 Chemical Mechanical Polishing 73 7.1.6 Thin Film Deposition 173 Physical Vapor Deposition(PVD) 175 Chemical Vapor Depositon(CVD) 176 7.2 CMOS Process Integration 177 FEOL 177 BEOL 77 CMOS Process Description 178 7. 2. 1 Frontend-of-the-Line Integration 180 Shallow Trench Isolation Module 181 Twin Tub module 187 Gate Module 190 Source/drain module 193 7.2.2 Backend-of-the-Line Integration 199 Self-Aligned Silicide(Salicide)Module 199 Pre-Metal dielectric 200 Contact Module 202 Metallization 1 203 Intra-Metal Dielectric 1 Deposition 205 Contents Via 1 Module 205 Metallization 2 207 Additional Metal/ Dieletric Layers 208 Final passivation 208 7. 3 Backend Processes 209 Wafer probe 209 Die Separation 211 Packaging 211 Final test and Burn -In 211 7.4 Summary 211 Chapter 8 Electrical Noise: An Overview 213 8.1 Signals 213 8.1.1 Power and Energy 213 Comments 215 8.1.2 Power Spectral density 215 Spectrum Analyzers 216 8.2 Circuit Noise 219 8.2.1 Calculating and Modeling Circuit Noise 219 Input-Referred noise l 220 Noise Equivalent Bandwidth 220 Input-Referred Noise in Cascaded Amplifiers 223 Calculating VonoiseRMs from a Spectrum: A Summary 224 8.2.2 Thermal noise 225 8. 2. 3 Signal-to-Noise Ratio 230 Input-Referred Noise I 23 Noise Figure 233 An Important Limitation of the Noise Figure 233 Optimum Source Resistance 236 Simulating Noiseless Resistors 236 Noise Temperature 239 Averaging white Noise 240 8.2. 4 Shot noise 242 8.2.5 Flicker Noise 244 8.2, 6 Other noise sources 252 Random Telegraph Signal Noise 252 Excess Noise(Flicker Noise) 253 Avalanche Noise 253

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    tx1004_02hxm 很好,很权威
    2020-08-07
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    xiedangui 很好,学习了
    2019-04-09
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