UM10470
LPC178x/7x User manual
Rev. 1.5 — 6 July 2011 User manual
Document information
Info Content
Keywords LPC1788FBD208, LPC1788FET208, LPC1788FET180,
LPC1788FBD144, LPC1787FBD208, LPC1786FBD208,
LPC1785FBD208, LPC1778FBD208, LPC1778FET208,
LPC1778FET180, LPC1778FBD144, LPC1777FBD208,
LPC1776FBD208, LPC1776FET180, LPC1774FBD208,
LPC1774FBD144, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, LCD,
CAN, I
2
C, I
2
S, Flash, EEPROM, Microcontroller
Abstract LPC178x/7x user manual
UM10470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 1.5 — 6 July 2011 2 of 1035
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors
UM10470
LPC178x/7x User Manual
Revision history
Rev Date Description
1.5 20110706 Added description of the Power Boost feature. Also other minor updates and corrections.
1.4 20110610 Official LPC178x/7x user manual release. Event Monitor/Recorder added. Minor updates
and corrections.
1.3 20110307 Replaced missing figure 10. Minor updates and corrections.
1.2 20110225 Removed SPIFI to reflect initial product release. Minor updates and corrections.
1.1 20110125 Minor updates and corrections.
1.0 20101022 First release of the LPC178x/7x User Manual.
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User manual Rev. 1.5 — 6 July 2011 3 of 1035
1.1 Introduction
The LPC178x/177x is an ARM Cortex-M3 based microcontroller for embedded
applications requiring a high level of integration and low power dissipation.
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at
the same clock rate, and offers other system enhancements such as modernized debug
features and a higher level of support block integration. The Cortex-M3 CPU incorporates
a 3-stage pipeline and has a Harvard architecture with separate local instruction and data
buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches. The LPC178x/177x adds a specialized flash memory accelerator to give
optimal performance when executing code from flash. The LPC178x/177x is targeted to
operate at up to a 120 MHz CPU frequency under worst case commercial conditions.
The peripheral complement of the LPC178x/177x includes up to 512 kB of Flash memory,
up to 96 kB of data memory, 4 kB of EEPROM memory, an External Memory Controller for
SDRAM and static memory access, an LCD panel controller, an Ethernet MAC, a General
Purpose DMA controller, a USB device/host/OTG interface, 5 UARTs, 3 SSP controllers, 3
I
2
C interfaces, an I
2
S serial audio interface, a 2-channel CAN interface, an SD card
interface, an 8 channel 12-bit ADC, a 10-bit DAC, a Motor Control PWM, a Quadrature
Encoder Interface, 4 general purpose timers, a 6-output general purpose PWM, an
ultra-low power RTC with separate battery supply and event monitor/recorder, a
windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins,
and more. The pinout of LPC178x/177x is intended to allow pin function compatibility with
the LPC24xx and LPC23xx.
UM10470
Chapter 1: Introductory information
Rev. 1.5 — 6 July 2011 User manual
UM10470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 1.5 — 6 July 2011 4 of 1035
NXP Semiconductors
UM10470
Chapter 1: Introductory information
1.2 Features
Refer to Section 1.4 for details of features for specific part numbers.
• Functional replacement for LPC23xx and 24xx family devices.
• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. The Cortex-M3
executes the Thumb®-2 instruction set for optimal performance and code size,
including hardware division, single cycle multiply, and bit-field manipulation. A
Memory Protection Unit (MPU) supporting eight regions is included.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
• Up to 96 kB on-chip SRAM includes:
– Up to 64 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, LCD, and DMA memory, as
well as for general purpose instruction and data storage.
– 4 kB on-chip EEPROM.
• External Memory Controller provides support for asynchronous static memory devices
such as RAM, ROM and Flash up to 64 MB, as well as dynamic memories such as
Single Data Rate SDRAM.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
2
S, UART, SD/MMC, CRC engine,
Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals,
GPIO, and for memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, LCD
controller, and the USB interface. This interconnect provides communication with no
arbitration delays unless two masters attempt to access the same slave at the same
time.
• Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
• LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays.
– Dedicated DMA controller.
– Selectable display resolution (up to 1024 × 768 pixels).
– Supports up to 24-bit true-color mode.
• Serial interfaces:
– Ethernet MAC with MII/RMII interface and dedicated DMA controller.
– USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
UM10470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 1.5 — 6 July 2011 5 of 1035
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UM10470
Chapter 1: Introductory information
– Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA
support, and RS-485/EIA-485 support. UART1 also has a full set of modem
handshaking signals. UART4 includes a synchronous mode and a Smart Card
mode supporting ISO 7816-3. Devices in the 144-pin package provide 4 UARTs.
– Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
– Three enhanced I
2
C-bus interfaces, one with an open-drain output supporting the
full I
2
C specification and Fast mode Plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
– Two-channel CAN controller.
– I
2
S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I
2
S interface can be used with the GPDMA. The I
2
S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
• Other peripherals:
– SD card interface that also supports MMC cards.
– General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open
drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast
access, and support Cortex-M3 bit-banding. GPIOs can be accessed by the
General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate
an interrupt. There are 165 GPIOs on 208-pin packages, 141 GPIOs on 180-pin
packages, and 109 GPIOs on 144-pin packages.
– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
– Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
– One motor control PWM with support for three-phase motor control.
– Quadrature encoder interface that can monitor one external quadrature encoder.
– Two standard PWM/timer blocks with external count input option.
– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
– Event Monitor/Recorder that can capture the RTC value when an event occurs on
any of 3 inputs. The event identification and the time it occurred are stored in
registers. The Event Monitor/Recorder is in the RTC power domain, and can
therefore operate as long as there is RTC power.
– Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal
oscillator, watchdog warning interrupt, and safety features.
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