UCIe White paper 2022

Property of Universal Chiplet Interconnect Express (UCIe) 2022

Universal Chiplet Interconnect Express (UCIe)®: Building an open chiplet ecosystem

Dr. Debendra Das Sharma

Intel Senior Fellow and Chief Architect, I/O Technologies and Standards

Promoter Member of UCIe

Motivation for on-package integration of Chiplets

In his seminal paper “Cramming more components onto integrated circuits” (published in

Electronics, Volume 38, Number 8, on April 19, 1965), Gordon Moore posited that the number of

transistors in an integrated circuit will double every two years. Popularly known as “Moore’s law”, it has

held up for more than 50 years thus far. In the same paper, Gordon Moore also predicted the “Day of

Reckoning”: “It may prove to be more economical to build large systems out of smaller functions, which

are separately packaged and interconnected.” Today we see on-package integration of multiple dies in

mainstream commercial offerings such as client CPUs, server CPUs, GP-GPUs, etc.

There are many drivers for on-package chiplets. As the die size increases to meet the growing

performance demands, designs are running up against the die reticle limit. Examples include multi-core

compute cores shown in Figure 1 can be implemented in an advanced process node to deliver

leadership power-efficient performance at higher cost whereas the memory and I/O controller

functionality may be reused from a design already deployed in an established (n-1 or n-2) process node.

Such partitioning also results in smaller dies which results in better yield. IP porting costs across process

nodes are high and increasing very rapidly for the advanced process nodes, as shown in Figure 2. Since

we don’t have to port all the IPs of dies whose functionality does not change, we save on costs in

addition to getting the time to market advantage. Chiplet integration on package also enables a

customer to make different trade-offs for different market segments by choosing different numbers and