Lattice_diamond指导手册.pdf

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软件lattice Diamond 使用官方指导手册,英文版,Lattice Diamond Tutorial
Type Conventions Used in This Document Convention Meaning or Use Bold Items in the user interface that you select or click. Text that you type into the user interface </talic> Variables in commands, code syntax, and path names Ctr+L Press the two keys at the same time Courier Code examples. Messages, reports, and prompts from the software Omitted material in a line of code Omitted lines in code and report examples Optional items in syntax descriptions In bus specifications, the brackets are required () Grouped items in syntax descriptions Repeatable items in syntax descriptions a choice between items in syntax descriptions Lattice Diamond tutorial Lattice Diamond Tutoria HLATCE Contents Lattice diamond tutorial 7 Learning Objectives 7 Time to Complete This Tutorial 8 System Requirements 8 Accessing Online Help and Diamond User Guide 9 About the Tutorial Design 9 About the tutorial data flow 9 Task 1: Create a New lattice diamond project 11 Task 2: Create an IPexpress Module 17 Task 3: Verify Functionality with Simulation 20 Task 4: Inspect Strategy Settings 22 Task 5: Examine resources 24 Task 6: Run Synthesis Process 27 Task 7: Set Timing and Location Assignments 28 Task 8: Running Place and Route 33 Task 9: Examine post place and route results 36 ask 10: Adjust Static Timing Constraints and Review Results 40 Task 11: Comparing Multiple Place and Route Runs 43 Task 12: Analyze power consumption 44 Task 13: Run Export Utility Programs 47 Task 14: Download a bitstream to an fpga 47 Task 15: Convert a File Using deployment Tool 49 ask 16: Use Reveal Inserter to Add On-chip Debug Logic 53 Setting Up the Trigger Units 55 Setting Up the Trigger Expressions 56 Inserting the Debug Logic 57 Generating a Bitstream and Programming the FPGa 59 Lattice Diamond tutorial CONTENTS Task 17: Use Reveal Logic Analyzer to Perform Logic Analysis 60 Creating a New Reveal Logic Analyzer Project 60 Running Logic Analyzer 63 Summary of Accomplishments 64 Recommended references 65 Lattice Diamond Tutoria HLATCE Lattice diamond tutorial The next generation design tool for FPGa design, Lattice Diamond M,is designed to address the needs of high-density FPGa designers This tutorial leads you through all the basic steps of designing and implementing a mixed VHDL, Verilog, and ediF design targeted to the LatticeECP3 device family. It shows you how to use several processes, tools, and reports from the lattice diamond software to import sources run design analysis, view design hierarchy, and inspect strategy settings. The tutorial then proceeds to step through the processes of adding and editing a strategy specifying the synthesis requirements, examining the device resources setting timing and location assignments, and editing preferences to configure the filter to implement the design to the target device Learning objectives When you have completed this tutorial, you should be able to do the following Create a new Lattice Diamond project Create an IPexpress module Verify functionality with simulation Inspect strategy settings Examine resources Run synthesis processes Set timing and location assignments Run place and route Examine post place and route results Adjust static timing constraints and review results Lattice Diamond tutorial LATTICE DIAMOND TUTORIAL Time to Complete This Tutorial Compare multiple place and route runs Analyze power consumption Run export utility programs download a bitstream to an fpga Convert a file using deployment Tool Use the reveal inserter to add on -chip debug logic Use the reveal logic analyzer to perform logic analysis Time to Complete This Tutorial The time to complete this tutorial is about 90 minutes System Requirements The following software is required to complete the tutorial Lattice Diamond software (Optional)LatticeECP3 Versa Development Kit Note The subscription version of Diamond software supports LatticeECP3 devices LatticeECP3 device support is disabled in the free version of Diamond software Users of the free version of Diamond software should request the " Diamond Free License-For Versa Kit Only. This license enables the user to select the LatticeECP3 LFE3-35EA device, which is required to perform the tutorial Many of the tasks in this tutorial can be performed without an actual lattice ECP3 Versa Development Kit, but the low-cost Lattice ECP3 Versa Development Kit is recommended to perform all of the tasks in this tutorial To download Diamond software, go to http://www.latticesemi.com/products/deSignSoftwareandip/fpgaandlds Lattice Diamond You must have a lattice web account to access this web page To obtain a Diamond Free License-For Versa kit only go to http://www.latticesemi.com/latticediamond#Tab6.YoumusthaveaLatticeweb account to access this web page To purchase a low-cost Lattice E CP3 Versa Development Kit, go to http://www.latticesemi.com/products/deveLopmentboardsandkits/ atticeECP3VersaDevelopmentKit aspx You must have a Lattice web account to access this web page Lattice Diamond Tutoria LATTICE DIAMOND TUTORIAL Accessing Online Help and Diamond User Guide Accessing Online Help and diamond User Guide You can find online help information on any tool included in the tutorial at any time by choosing Help Lattice Diamond help Another excellent resource is the diamond User guide, available from the start page of Lattice Diamond online help About the Tutorial Design The design in this tutorial consists of a verilog hdl module, two hdl modules, and one ediF module. the design that you create is targeted to Latticeecp3 device families About the tutorial data flow Figure 1 illustrates the tutorial data flow through the system. You may find it helpful to refer to this diagram as you move through the tutorial tasks Lattice Diamond tutorial LATTICE DIAMOND TUTORIAL About the tutorial data flow Figure 1: Tutorial Data Flow Create Project g Files File ALDEC Active-HDL Lattice edition Perform functional simulation Create a lattice P Add signals Examine Module esources EXpress Waveform viewer Synthesize Design Inspect Strategy Settings Translate and Map design Set Timing and location Assignments Place& route analyze Design Consumption Generate △| View Post Pla ace an Adjust Static Timing Route results Constraints and Review Bitstream Results Download bitstream with bit file Programmer Add On-chip Run/Debug hardware on Reveal inserter Debug Logic Board with Reveal analyzer Improve Hardware Reveal Inserter/Analyzer Lattice Diamond Tutoria

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