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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

3-1

3 ARM INSTRUCTION SET

INSTRUCTION SET SUMMAY

This chapter describes the ARM instruction set in the ARM920T core.

FORMAT SUMMARY

The following figure shows the ARM instruction set.

Cond Rn Data/Processing/

PSR Transfer

0 0 I S

Opcode

000PU0WL

000PU1WL

01IPUBWL

01I

100PUBWL

11 11 1 1 11

10 L1

110PUBWL

11 11

11 01

11 01 L

RnRdHi RdLo

Rn Register List

CRn

CRd

CP Opc

Opc

Operand2

Offset Offset

CRd OffsetCP#

CP#

CRm

Ignored by processor

Offset

Cond

0000 00 AS

ASU100 00

000 0 001 B

1 00 01000

Multiply

Multiply Long

Single Data Swap

Branch and Exchange

Halfword Data Transfer:

immendiate offset

Single Data Transfer

Undefined

Block Data Transfer

Branch

Coprocessor Register Transfer

Coprocessor Data Operation

Coprocessor Data Transfer

Software Interrupt

Offset

272625242322212019181716151314121110 313029289876543210

Figure 3-1. ARM Instruction Set Format

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

3-2

NOTES

Some instruction codes are not defined but does not cause Undefined instruction trap to be taken, for

instance a multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their

action may change in future ARM implementations.

INSTRUCTION SUMMARY

Table 3-1. The ARM Instruction Set

Mnemonic Instruction Action

ADC Add with carry Rd: = Rn + Op2 + Carry

ADD Add Rd: = Rn + Op2

AND AND Rd: = Rn AND Op2

B Branch R15: = address

BIC Bit clear Rd: = Rn AND NOT Op2

BL Branch with link R14: = R15, R15: = address

BX Branch and exchange R15: = Rn, T bit: = Rn[0]

CDP Coprocessor data processing (Coprocessor-specific)

CMN Compare Negative CPSR flags: = Rn + Op2

CMP Compare CPSR flags: = Rn - Op2

EOR Exclusive OR Rd: = (Rn AND NOT Op2)

OR (Op2 AND NOT Rn)

LDC Load coprocessor from memory Coprocessor load

LDM Load multiple registers Stack manipulation (Pop)

LDR Load register from memory Rd: = (address)

MCR Move CPU register to coprocessor

cRn: = rRn {<op>cRm}

MLA Multiply accumulate Rd: = (Rm × Rs) + Rn

MOV Move register or constant Rd: = Op2

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

3-3

Table 3-1. The ARM Instruction Set (Continued)

Mnemonic Instruction Action

MRC Move from coprocessor register to

CPU register

Rn: = cRn {<op>cRm}

MRS Move PSR status/flags to register Rn: = PSR

MSR Move register to PSR status/flags PSR: = Rm

MUL Multiply Rd: = Rm × Rs

MVN Move negative register Rd: = 0 × FFFFFFFF EOR Op2

ORR OR Rd: = Rn OR Op2

RSB Reverse subtract Rd: = Op2 - Rn

RSC Reverse subtract with Carry Rd: = Op2 - Rn - 1 + Carry

SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry

STC Store coprocessor register to memory address: = CRn

STM Store Multiple Stack manipulation (Push)

STR Store register to memory <address>: = Rd

SUB Subtract Rd: = Rn - Op2

SWI Software Interrupt OS call

SWP Swap register with memory Rd: = [Rn], [Rn] := Rm

TEQ Test bitwise equality CPSR flags: = Rn EOR Op2

TST Test bits CPSR flags: = Rn AND Op2

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

3-4

THE CONDITION FIELD

In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the

instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be

executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is

executed, otherwise it is ignored.

There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the

instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which

means the Branch will only be taken if the Z flag is set.

In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved,

and must not be used.

In the absence of a suffix, the condition field for most instructions is set to "Always" (suffix AL). This means the

instruction will always be executed regardless of the CPSR condition codes.

Table 3-2. Condition Code Summary

Code Suffix Flags Meaning

0000 EQ Z set equal

0001 NE Z clear not equal

0010 CS C set unsigned higher or same

0011 CC C clear unsigned lower

0100 MI N set negative

0101 PL N clear positive or zero

0110 VS V set overflow

0111 VC V clear no overflow

1000 HI C set and Z clear unsigned higher

1001 LS C clear or Z set unsigned lower or same

1010 GE N equals V greater or equal

1011 LT N not equal to V less than

1100 GT Z clear AND (N equals V) greater than

1101 LE Z set OR (N not equal to V) less than or equal

1110 AL (ignored) always

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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

3-5

BRANCH AND EXCHANGE (BX)

This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.

This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter, PC.

The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the

instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the

instruction stream will be decoded as ARM or THUMB instructions.

31 2427 19 15 87 0

00 0 1 10 0 0 11 1 1 11 1 1 11 1 1 00 0 1Cond Rn

28 16 111223 20 43

[3:0] Operand Register

If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions

If bit0 of Rn =0, subsequent instructions decoded as ARM instructions

[31:28] Condition Field

Figure 3-2. Branch and Exchange Instructions

INSTRUCTION CYCLE TIMES

The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and non-

sequential (N-cycle), respectively.

ASSEMBLER SYNTAX

BX - branch and exchange.

BX {cond} Rn

{cond} Two character condition mnemonic. See Table 3-2.

Rn is an expression evaluating to a valid register number.

USING R15 AS AN OPERAND

If R15 is used as an operand, the behavior is undefined.

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