TMS320C6678数据手册

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TMS320C6678数据手册,在对6678的中断配置,时钟配置等方面具有指导意义。
中 TEXAS INSTRUMENTS TMs320c6678 Multicore Fixed and Floating-Point Digital Signal Processor www.ti.com SPRS691C-February 2012 Contents 1 Features ·······.···:.·:·..:.··....······ 1.1 KeyStone Architecture................. ∴,,,,,,,14 1.2 Device Description 14 1.3 Functional Block Diagram.,...,........... :·· 16 2 Device overview∴, ··.· 17 2.1 Device Characteristics 2.2 DSP Core Description ..18 2.3 Memory Map Summary. 2. 4 Boot Sequence 2.5 Boot Modes Supported and PLL Se 28 2.5.1 Boot Device field 2.5.2 Device Configuration Field 29 2.5.3 PLL Boot Configuration Settings 34 2.6 Second-Level bootloaders 34 27 Terminals 35 2.7.1 Package Terminals 2.7.2 Pin Map 2.8 Terminal Functions 29 Development and Support∴……, 2.9.1 Development Support 64 2.9.2 Device Support.......,.............. 2.10 Related Documentation from Texas Instruments.……∴……∴… ,66 3 Device Confiquration 67 3.1 Device Configuration at device reset ∴..67 3.2 Peripheral Selection After Device Reset 68 3.3 Device State Control Registers 68 3.3.1 Device Status Register 72 3.3.2 Device Confiquration Register ··· 3.3.3 JTAG ID (JTAGID) Register Description 73 3.3.4 Kicker Mechanism(KICKo and KiCK1) Register. 74 3.3.5 LRESETNMI PIN Status(LRSTNMIPINSTAT) Register 74 3.3.6 LRESETNMI PIN Status Clear(LRSTNMIPINSTAT_CLR)Register 3.3.7 Reset Status(RESET_ STAT)Register.................. ,,·,·,···,· 338 Reset Status Clear( RESET STAT CLR) Register∴…… 3.3.9 Boot Complete(BOOTCOMPLETE) Register 3.3.10 Power State Control (PWRSTATECTL)Register......,.............. 3.3.11 NMI Even Generation to CorePac(NMIGRx) Register 3.3. 12 IPC Generation (IPCGRX) Registers 3.3.13 IPC Acknowledgement(IPCARx) Registers 81 3.3.14 PC Generation Host (PCGRH) Register ·· 3.3.15 IPC Acknowledgement Host(IPCARH) Register 82 3.3.16 Timer Input Selection Register(TINPSEL).............................................. 8 3.3. 17 Timer Output Selection Register (TOUTPSEL).............. ·· 3.3.18Re (RSTMUXX) Regi 3.3. 19 Device Speed(DEVSPEED) Register.................. ∴.88 3.4 Pullup/Pulldown Resistors 89 System Interconnect 90 4.1 Internal buses and switch fabrics 90 4.2 Switch Fabric Connections ··t、,重 4.3 Bus Priorities 99 5 C66x Corea 100 5.1 Memory Architecture. 垂看 101 5.1.1 L1P Memory 101 5.1.2 LID Memory · 02 5.1.3L2M 103 Copyright 2012 Texas Instruments Incorporated Contents 3 TMs320c6678 中 SEXAS Multicore Fixed and Floating-Point Digital Signal Processor INSTRUMENTS SPRS691C-February 2012 www.ti.com 5.1.4 MSM SRAM .104 5.1.5 L3 Memory 104 5.2 Memory protection ∴,105 5.3 Bandwidth Management .106 5.4 Power-Down Control 5.5 C66x Core Pac Revision 107 56C66 k CorePac Register Descriptions.…… 107 6 Device Operating Conditions ∴,108 6.1 Absolute Maximum Ratings....,.....,.. ,,108 6.2 Recommended Operating Conditions....,................ 6.3 Electrical Characteristics 110 6.4 Power Supply to Peripheral l/O Mapping 7 Peripheral Information and Electrical Specifications.......... ,,,112 7.1 Recommended Clock and Control Signal Transition Behavior............. 112 7.2 Power Supplies......,........ 112 7. 2. 1 Power-Supply sequencing 113 7.2.2 Power-Down Sequence..........,. 118 7. 2.3 Power Supply decoupling and Bulk Capacitors 118 7. 2.4 SmartReflex 119 7.3 Power Sleep controller(PSo) 120 73.1 Power domains 120 7.3.2 Clock domains 121 73.3 PSC Register Memory Map∴…… ∴,122 7.4 Reset controller 124 74.1 Power-on re 125 7.4.2 Hard reset 126 74.3 Soft re 74.4 Local reset 128 7.4.5 Reset Priority 7.4.6 Reset Controller register... 128 7.4.7 Reset Electrical Data /Timing............ 7.5 Main pll and pll controlle 7.5.1 Main PLL Controller Device-Specific Information 132 7.5.2 PLL Controller Memory map 134 7.5.3 Main PLL Control regist ,,,,140 14 ...141 143 7.6.1 DDR3 PLL Control Register.. ·· 144 7.6.2 DDR3 PLL Device-Specific Information.... 7.6.3 DDR3 PLL Initialization Sequence 145 7.6.4 DDR3 PLL Input Clock Electrical Data/Timing............ 145 7.7 PASS PL .147 7.7. 1 PASS PLL Control Register........... .147 7.7.2 PASS PLL Device-Specific Information 148 7.7.3 PASS PLL Initialization Sequence 148 7.7.4 PASS PLL Input Clock Electrical Data/Timing 149 7. 8 Enhanced Direct Memory Access(EDMA3) Controller :.· 7.8.1 EDMA3 Device-Specific Information ··.·;;·· ·.· ,,150 7.8.2 EDMA3 Channel Controller Configuration 151 7.8.3 EDMA3 Transfer Controller Configuration.................... ∴..,151 7.8.4 EDMA3 Channel Synchronization Events 152 7.9 Interrupts 155 7.9.1 Interrupt Sources and Interrupt Controller ∴.155 7.9.2 CIC Registers 174 7.9.3 Inter-Processor Register Map 7.9.4 NMI and reset ∴180 7.9.5 External Interrupts Electrical Data/Timing 垂 垂·· 着垂c ∴.,,181 4 Contents Copyright 20 12 Texas Instruments Incorporated 中 TEXAS INSTRUMENTS TMs320c6678 Multicore Fixed and Floating-Point Digital Signal Processor www.ti.com SPRS691C-February 2012 7.10 Memory Protection Unit(MPU 182 7.10.1 MPU Registers .185 7.10.2 MPU Programmable range registers 7.11 DDR3 Memory Controller ..195 7.11.1 DDR3 Memory Controller Device-Specific Information 7.11.2 DDR3 Memory Controller Electrical Data/Timing 7. 12 I-C Peripheral 垂垂 7.12.112C Device-Specific Information 196 7.12.2 12C Peripheral Register Description(s) 197 7. 12.3 1C Electrical Data/Timing 198 7.13 SPI Peripheral... 201 7.13.1 SPI Electrical Data/Timing 201 7.14 HyperLink Peripheral.,. 204 7. 14.1 HyperLink Device-Specific Interrupt Event 204 7.14.2 HyperLink Electrical Data/Timing 206 7.15 UART Peripheral...,.,...,..... 208 7.16 PCle Peripheral 209 7.17 TSIP Peripheral.……… 210 7.17.1 TSIP Electrical Data/Timing 210 7.18 EMIF16 Peripheral ··面··面 ,,212 7. 18.1 EMIF16 Electrical Data/Timing........... .212 7. 19 Packet Accelerator 214 7.20 Security Accelerator 4 7.21 Gigabit Ethernet(GbE)Switch Subsystem 215 7.2 Management Data Input/ Output(MDlO).…,……,,,,,, 217 7. 23 Timer 218 7. 23.1 Timers Device-Specific Information “·;·“· 218 7.23. 2 Timers Electrical Data/Timing 和垂 218 7. 24 Serial RapidIo (SRIO)Port.............. 219 7. 25 General-Purpose Input/Output(GPIO)........... 220 7. 25.1 GPlO Device-Specific Information ..220 7.25.2 GPIO Electrical Data/Timing 7.26 Semaphore 2 .221 7.27 Emulation Features and Capability........ 7. 27.1 Advanced Event Triggering(Aet) ,,221 7. 27.2 Trace 221 7,27.3|EEE11491JAG ·.·...··· a Revision History.… 224 B Mechanical data ··; 227 B. 1 Thermal Data B2 Packaging Information....... 07 Copyright 2012 Texas Instruments Incorporated Contents 5 TMs320c6678 SEXAS Multicore Fixed and Floating-Point Digital Signal Processor INSTRUMENTS SPRS691C-February 2012 www.ti.com List of Figures Figure 1-1 Functional Block Diagram .16 Figure 2-1 DSP Core data Paths Figure 2-2 boot mode pin decoding ;。;· 28 Figure 2-3 No Boot/EMIF16 Configuration Fields ··:···.··· .29 Figure 2-4 Serial Rapid V/O Device Configuration Fields Figure 2-5 Ethernet(SGMID)Device Configuration Fields............. Figure 2-6 PCI Device Configuration Fields 30 Figure 2-7 1C Master Mode Device Configuration Bit Fields Figure 2-8 C Passive Mode Device Configuration Bit Fields .32 Figure 2-9 SPI Device Contiguration Bit Fields · .32 Figure 2-10 HyperLink Boot Device Configuration Fields 33 Figure 2-11 CYP 841-Pin BGA Package(Bottom View) 35 Figure 2-12 Pin Map Quadrants(Bottom view) Figure 2-13 Upper Left Quadrant-A (Bottom View) ∴∴36 Figure 2-14 Upper Right Quadrant--B(Bottom View ). 7 Figure 2-15 Lower Right Quadrant-C(Bottom View) .38 Figure 2-16 Lower Left Quadrant-D (Bottom View) ∴.39 Figure 2-17 C66x DSP Device Nomenclature(including the TMS320C6678 65 Figure 3-1 Device Status Register....,..... Figure 3-2 Device Configuration Register (DEVCFG) ∴..73 Figure 3-3 JTAG ID (TAGID) Register 73 Figure 3-4 LRESETNMI PIN Status Register(LRSTNMIPINSTAT) 74 Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR Figure 3-6 Reset Status Register(RESET_ STAT 76 Figure 3-7 Reset Status Clear Register(RESET_ STAT- Clr) ∴,77 Figure 3-8 boot Complete register ( bootcomPlete 78 Figure 3-9 Power State Control Register(PWRSTATECTL) 79 Figure 3-10 NMI Generation Register(NMIGRx) 79 Figure 3-11 IPC Generation Registers(IPCGRx Figure 3-12 IPC Acknowledgement Registers (IPCARX) Figure 3-13 IPC Generation Registers(IPCGRH) ·····.·· Figure 3-14 IPC Acknowledgement Register(IPCARH Figure 3-15 Timer Input Selection Register(TINPSEL .83 Figure 3-16 Timer Output Selection Register (TOUTPSEL) .86 Figure 3-17 Reset Mux Register RSTMUXX Figure 3-18 Device Speed Register(DEVSPEED) ∴.88 Figure 4-1 TeraNet 2A for C6678..............................................91 Figure 4-2 TeraNet 3A for C6678 Figure 4-3 TeraNet 3P_a& B for C6678 94 Figure 4-4 TeraNet 6P_B and 3P_Tracer for C6678 Figure 4-5 Packed DMA Priority Allocation Register(PKTDMA_PRL_ALLoC) 99 Figure 5-1 C66x Core Pac Block Diagram ∴.100 Figure 5-2 L1 P Memory Configurations .101 Figure 5-3 L1D Memory Configurations .102 Figure 5-4 L2 Memory Configurations......,.... ,,103 Figure 5-5 Core Pac Revision ID Register (MM_REviD)Address-0181 2000h .107 Figure 7-1 Core before lo Power Sequencing ··· 114 Figure 7-2 IO Before Core Power Sequencing 116 Figure 7-3 SmartReflex 4-Pin VID Interface Timing 119 Figure 7-4 RESETFULL Reset Timing......... .,129 Figure 7-5 Soft/Hard-Reset Timing.......................... .,129 6 List of Figures Copyright 2012 Texas Instruments Incorporated 中 TEXAS INSTRUMENTS TMs320c6678 Multicore Fixed and Floating-Point Digital Signal Processor www.ti.com SPRS691C-February 2012 Figure 7-6 Boot Configuration liming 130 Figure 7-7 Main PLl and PLl Controller 131 Figure 7-8 PLL Secondary Control register(SECCTL)) .135 Figure 7-9 PLL Controller Divider Register(PLLDIVn 136 Figure 7-10 PLL Controller Clock Align Control Register(ALNCTL) ,,136 Figure 7-11 PLLDIV Divider Ratio Change Status Register (DCHANGE) 137 Figure 7-12 SYSCLK Status Register(SYSTAT) 137 Figure 7-13 Reset Type Status Register(RSTYPE). ·垂 138 Figure 7-14 Reset Control Register(RSTCTRl) 138 Figure 7-15 Reset Configuration Register(RSTCFG) ,139 Figure7-16 Reset Isolation Register(RSsO)..…..…… ∴,140 Figure 7-17 Main PLl Control Register O (MAINPLLCTLO ..140 Figure 7-18 Main PLL Control Register 1(MAINPLLCTL1 Figure 7-19 Main PLL Controller/SRIO/HyperLink/PCle Clock Input Timing .143 Figure 7-20 Main PLL Clock Input transition Time ,143 Figure 7-21 DDR3 PLL Block Diagram Figure 7-22 DDR3 PLL Control Register O(DDR3PLLCTLO) igure 7-23 DDR3 PLL Control Register 1(DDR3PLLCTL1) Figure 7-24 DDR3 PLL DDRCLK T iming 146 Figure 7-25 PASS PLL Block Diagram....... ..147 Figure 7-26 PASS PLL Control Register O(PASSPLLCTLO) ,147 Figure 7-27 PASS PLL Control Register 1(PASSPLLCTL1) ,.,148 Figure 7-28 PASS PLL Timing........... 149 Figure 7-29 TMS320C6678 Interrupt Topology 157 Figure 7-30 NMI and Local reset Timing 181 Figure 7-31 Configuration Register (CONFIG) 189 Figure 7-32 Programmable Range n Start Address Register(PROGn_MPSar)......................... 190 Figure 7-33 Programmable range n End Address Register(Progn MPEAr)....,...,.... ∴,191 Figure 7-34 Programmable Range n Memory Protection Page Attribute Register( PROGn_MPPA 192 Figure 7-35 |2C Module Block Diagram ∴.,197 Figure 7-36 IC Receive Timings........ 199 Figure 7-37 1C Transmit Timings 200 Figure 7-38 SPI Master Mode Timing Diagrams-Base Timings for 3 Pin Mode. ......................., 203 Figure 7-39 SPI Additional Timings for 4 Pin Master Mode with Chip Select Option ∴.,203 Figure 7-40 HyperLink Station Management Clock Timing ∴,207 Figure 7-41 HyperLink Station Management Transmit Timing 207 Figure 7-42 HyperLink Station Management Receive Timing.......................... 207 Figure 7-43 UART Receive Timing Waveform 208 Figure 7-44 UART CTS(Clear-to-Send Input)-Autoflow Timing Waveform 208 Figure 7-45 UART Transmit Timing Waveform 209 igure 7-46 UART RTS(Request-to-Send Output)-Autoflow Timing Waveform. Figure 7-4 TSIP 2x Timing Diagram(1) 210 Figure 7-48 TSIP 1x Timing Diagram(1) 211 Figure 7-49 EMIF 16 Asynchronous Memory Read Timing Diagram .,213 Figure 7-50 EMIF16 Asynchronous Memory Write Timing Diagram 213 Figure 7-51 EMIF 16 EM_WAIT Read Timing Diagram .214 Figure 7-52 EMIF16 EM_WAIT Write Timing Diagram 214 Figure7-53MAc|D1 Register∴… ·+ 215 Figure 7-54 MACID2 Register 215 Figure 7-55 CPTS_RFTCLK- SEL Register 216 Figure 7-56 MDIO Input Timing 217 Figure 7-57 MDIO Output Timing 217 Figure 7-58 Timer Timing. ··:······.·.;··;;.··.···.·.·.··;··..··;: 219 Figure 7-59 GPlO Timing.......,..... ,,,220 Copyright 2012 Texas Instruments Incorporated List of Figures 7 TMs320c6678 中 SEXAS Multicore Fixed and Floating-Point Digital Signal Processor INSTRUMENTS SPRS691C-February 2012 www.ti.com Figure 7-60 Trace Timing Figure 7-61 JTAG Test-Port Timing 223 8 List of Figures Copyright 2012 Texas Instruments Incorporated 中 TEXAS INSTRUMENTS TMs320c6678 Multicore Fixed and Floating-Point Digital Signal Processor www.ti.com SPRS691C-February 2012 List of tables Table 2-1 Device characteristics ..17 Table 2-2 Memory Map summary.. ∴∴21 Table 2-3 Boot mode pins: Boot device values 28 Table 2-4 No Boot/EMIF16 Configuration Field Descriptions ··:·;· 29 Table 2-5 Serial Rapid /0 Configuration Field Descriptions Table 2-6 Ethernet (SGMID) Configuration Field Descriptions 垂·南 Table 2-7 PCI Device Configuration Field Descriptions........... 30 Table 2-8 BAR Config /pcle Window Sizes Table 2-9 I<C Master Mode Device Configuration Field Descriptions Table 2-10 IC Passive Mode Device Configuration Field Descriptions ..32 Table 2-11 SPl Device Configuration Field Descriptions ··. 32 Table 2-12 Hyper Link Boot Device Configuration Field Descriptions. 33 Table 2-13 C66x DSP System PLL Configuration Table 2-14 I/O Functional Symbol Definitions Table 2-15 Terminal functions- Signals and Control by function 40 Table 2-16 Terminal functions -Power and ground .52 Table 2-17 Terminal Functions - By Signal Name ..53 Table 2-18 Terminal Functions -By Ball Number 57 Table3-1 TMS320C6678 Device Configuration Pins 67 Table 3-2 Device State Control Registers ...... ∴.,68 Table 3-3 Device Status Register Field Descriptions Table 3-4 Device Configuration Register Field Descriptions 73 Table 3-5 JTAG ID Register Field Descriptions 73 Table 3-6 LRESETNMI PIN Status Register(LRSTNMIPINSTAT) Field Descriptions 74 Table 3-7 LRESETNMI PIN Status Clear Register(LRSTNMIPINSTAT_CLR) Field Descriptions ∴.75 Table 3-8 Reset Status Register (RESET_STAT) Field Descriptions 普b面 76 Table 3-9 Reset Status Clear Register(RESET_STAT_CLR) Field Descriptions ∴77 Table 3-10 Boot Complete Register(BOOTCOMPLETE) Field Descriptions 78 Table 3-11 Power State Control Register(PWRStaTECTL) Field Descriptions 垂着 79 Table 3-12 NMI Generation Register(NMIGRx)Field Descriptions Table 3-13 IPC Generation Registers(IPCGRx) Field Descriptions ·· Table 3-14 IPC Acknowledgement Registers(IPCARx) Field Descriptions Table 3-15 IPC Generation Registers(IPCGRH)Field Descriptions Table 3-16 IPC Acknowledgement Register(IPCARH) Field Descriptions Table 3-17 Timer Input Selection Field Description(TINPSEL .83 Table 3-18 Timer Output Selection Field Description (TOUTPSEL ∴86 Table 3-19 Reset Mux Register Field Descriptions......... 87 Table 3-20 Device Speed Register Field Descriptions Table 4-1 Switch Fabric Connection matrix Section 1 Table 4-2 Switch fabric connection matrix Section 2 Table 4-3 Switch Fabric Connection Matrix Section 3 .97 Table 4-4 Packed DMA Priority Allocation Register(PKTDMA PRI ALLOC)Field Descriptions Table 5-1 Available Memory Page Protection Schemes 105 Table 5-2 CorePac Revision ID Register(MM Table 6-1 Absolute Maximum Ratings .,108 Table 6-2 Recommended Operating Conditions ....109 Table 6-3 E| ectrical Characteristics………… 110 Table 6-4 Power Supply to Peripheral l/0 Mapping 111 Table 7-1 Power Supply Rails on TMS320C6678 112 Table 7-2 Core Before IO p。 wer Sequencing∴… ∴.,115 Table 7-3 O Before Core Power Sequencing∴…………… ..117 Copyright 2012 Texas Instruments Incorporated List of tables 9 TMs320c6678 中 SEXAS Multicore Fixed and Floating-Point Digital Signal Processor INSTRUMENTS SPRS691C-February 2012 www.ti.com Table 7-4 Clock Sequencing 118 Table 7-5 SmartReflex 4-Pin VID Interface Switching Characteristics 119 Table 7-6 Power domains 120 Table 7-7 Clock domains Table 7-8 PSC Register Memory Map ,,,122 Table 7-9 Reset Iypes ...124 Table 7-10 Reset Timing Requirements 129 Table 7-11 Reset Switching Characteristics Over Recommended Operating Conditions.................... 129 Table 7-12 Boot Configuration Timing Requirements 130 Table 7-13 Main pll stabilization lock and reset times ..133 Table 7-14 PLL Controller Registers (Including Reset Controller ∴134 Table 7-15 PLL Secondary Control Register(SECCTL) Field Descriptions .135 Table 7-16 PLL Controller Divider Register(PLLDIVn) Field Descriptions............ 136 Table 7-17 PLL Controller Clock Align Control Register(ALNCTL) Field Descriptions. 136 Table 7-18 PLLDIV Divider Ratio Change Status Register(DCHANGE) Field Descriptions ∴,,137 Table 7-19 SYScLK Status Register(SYsTAT) Field Descriptions ...137 Table 7-20 Reset Type Status Register(RSTYPE) Field Descriptions 138 Table 7-21 eset Control Register(RStCtRl) Field Descriptions .139 Table 7-22 Reset Configuration Register(rStCFG) Field Descriptions 139 Table 7-23 Reset Isolation Register(RSISO) Field Descriptions 140 Table 7-24 Main PLL Control Register O (MAINPLLCTLO)Field Descriptions.......................... 141 Table 7-25 Main PLL Control Register 1(MAINPLLCTL1)Field Descriptions. Table 7-26 Main PLL Controller/SRIO/HyperLink/PCle Clock Input Timing Requirements ................... 141 Table 7-27 DDR3 PLL Control Register O Field Descriptions Table 7-28 DDR3 PLL Control Register 1 Field Descriptions........ 145 Table 7-29 DDR3 PLL DDRSYSCLKI(NP) Timing Requirements 145 Table 7-30 PASS PLL Control Register 0 Field Descriptions Table 7-31 PASS PLL Control Register 1 Field Descriptions.......,........,..... 148 Table 7-32 PASS PLl Timing requirements 149 Table 7-33 EDMA3 Channel Controller Configuration Table 7-34 EDMA3 Transfer Controller Configuration ∴.15 Table 7-35 EDmA3CC0 Events for c6678 152 Table 7-36 edma3CC1 Events for c6678 ······,········ ∴152 Table 7-37 EDMA3CC2 Events for C6678 Table 7-38 TMS320C6678 System Event Mapping-C66x CorePac Primary Interrupts.................... 158 Table 7-39 CICO Event Inputs(Secondary Interrupts for C66x Core Pacs …161 Table 7-40 ClC1 Event Inputs(Secondary Interrupts for C66x CorePacs 165 Table 7-41 ClC2 Event Inputs(Secondary Events for EDMA3 CCl and EDMA3CC2 169 Table 7-42 CIC3 Event Inputs(Secondary Events for EDMA3CCO and HyperLink) 172 Table 7-43 CICo/CIC1 Register...........,... ..174 Table 7-44 ClC2 Register ∴,176 Table 7-45 CIC3 Register 178 Table 7-46 IPC Generation Registers(IPCGRX .,179 Table 7-47 LRESET and NMI Decoding........... .180 Table 7-48 NMI and Local reset Timing Requirements 181 Table 7-49 MPU Default Configuration ·4“垂鲁垂“垂,垂 Tabe7-50 MPU Memory Regions∴… Table 7-51 Privilege ID Settings........... 182 Table 7-52 Master ID Settings Table 7-53 MPUO Registers Table 7-54 MPU1 Registers 186 Table 7-55 MPU2 Registers 187 Table 7-56 MPU3 Registers :..·······;·.·· :· Table 7-57 Configuration Register(CoNFIG)Field Descriptions............... .189 10 List of tables Copyright 2012 Texas Instruments Incorporated

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