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SNUG Silicon Valley 2013 1 Synthesizing SystemVerilog

Synthesizing SystemVerilog

Busting the Myth that SystemVerilog is only for Verification

ABSTRACT

SystemVerilog is not just for Verification! When the SystemVerilog standard was first devised, one

of the primary goals was to enable creating synthesizable models of complex hardware designs

more accurately and with fewer lines of code. That goal was achieved, and Synopsys has done a

great job of implementing SystemVerilog in both Design Compiler (DC) and Synplify-Pro. This

paper examines in detail the synthesizable subset of SystemVerilog for ASIC and FPGA designs,

and presents the advantages of using these constructs over traditional Verilog. Readers will take

away from this paper new RTL modeling skills that will indeed enable modeling with fewer lines

of code, while at the same time reducing potential design errors and achieving high synthesis

Quality of Results (QoR).

Target audience: Engineers involved in RTL design and synthesis, targeting ASIC and FPGA

implementations.

Note: The information in this paper is based on Synopsys Design Compiler (also called HDL Compiler)

version 2012.06-SP4 and Synopsys Synplify-Pro version 2012.09-SP1. These were the most current

released versions available at the time this paper was written.

Stuart Sutherland

Sutherland HDL, Inc.

stuart@sutherland-hdl.com

Don Mills

Microchip Technology, Inc.

mills@microchip.com

SNUG Silicon Valley 2013 2 Synthesizing SystemVerilog

Table of Contents

1. Data types .................................................................................................................................4

1.1 Value sets ......................................................................................................................5

1.2 Net types .......................................................................................................................6

1.3 Variable types ...............................................................................................................6

1.4 Vector declarations (packed arrays) ..............................................................................6

1.5 Arrays (unpacked arrays) ..............................................................................................7

1.6 User-defined types ........................................................................................................9

2. Parameterized models .............................................................................................................13

3. Shared declaration spaces — packages and $unit ...................................................................14

3.1 Packages ......................................................................................................................14

3.2 $unit ............................................................................................................................16

4. RTL programming ..................................................................................................................17

4.1 Procedural blocks ........................................................................................................17

4.2 Operators .....................................................................................................................20

4.3 Casting ........................................................................................................................22

4.4 Decision statements ....................................................................................................23

4.5 Loop statements ..........................................................................................................26

4.6 Tasks and functions ....................................................................................................27

5. Module ports (internal to a module) .......................................................................................29

6. Netlists ....................................................................................................................................30

7. Interfaces .................................................................................................................................31

8. Miscellaneous synthesizable SystemVerilog constructs .........................................................33

8.1 Ending names ..............................................................................................................33

8.2 ‘begin_keywords and ‘end_keywords .......................................................................34

8.3 Vector fill tokens ........................................................................................................35

8.4 Constant variables (const) ...........................................................................................36

8.5 timeunit and timeprecision ..........................................................................................36

8.6 Expression size functions ($clog2, $bits) ...................................................................36

8.7 Assertions ....................................................................................................................37

9. Other synthesizable constructs ................................................................................................38

10. Difference between Design Compiler and Synplify-Pro ........................................................38

11. Wish List and Recommendations ...........................................................................................39

11.1 uwire single source nets ..............................................................................................39

11.2 Foreach loops ..............................................................................................................40

11.3 Task/function inputs with defaults ..............................................................................40

11.4 Task/function ref arguments .......................................................................................41

11.5 Set membership operator (inside) with expressions ...................................................42

11.6 Package chaining ........................................................................................................42

11.7 Extern module declarations ........................................................................................43

11.8 Configurations ............................................................................................................43

11.9 User-defined net types and generic net types .............................................................43

12. Summary .................................................................................................................................43

13. Acknowledgements .................................................................................................................44

14. References ...............................................................................................................................44

SNUG Silicon Valley 2013 3 Synthesizing SystemVerilog

1.0 Introduction — debunking the Verilog vs. SystemVerilog myth

There is a common misconception that “Verilog” is a hardware modeling language that is synthesizable,

and “SystemVerilog” is a verification language that is not synthesizable. That is completely false!

Verilog was first introduced in 1984 as a dual-purpose language to be used to both model hardware

functionality and to describe verification testbenches. Many of the Verilog language constructs, such as

if...else decision statements, were intended to be used for both hardware modeling and verification. A

number of the original Verilog constructs were intended strictly for verification, such as the

$display

print statement, and have no direct representation in hardware. Synthesis is concerned with the hardware

modeling aspect of the language, and therefore only supports a subset of the original Verilog language.

The IEEE officially standardized the Verilog language in 1995, with the standards number 1364-1995,

nicknamed Verilog-1995 [1].The IEEE then began work on extending the language for both design and

verification, and in 2001 released the 1364-2001 standard, commonly referred to as Verilog-2001 [2]. A

year later, the IEEE published the 1364.1-2002 Verilog RTL Synthesis standard [3], which defined the

subset of Verilog-2001 that should be considered synthesizable.

The IEEE also updated the Verilog standard, as 1364-2005, aka Verilog-2005 [4]. However, Integrated

Circuit functionality, complexity, and clock speeds evolved so rapidly in the 2000s, that an incremental

update to the Verilog standard was not going to be enough to keep pace with the continually greater

demand on the language capability to represent both hardware models and verification testbenches. The

new features that the IEEE specified to enhance the Verilog language were so substantial that the IEEE

created a new standards number, 1800-2005, and a new nickname, SystemVerilog [5], just to describe the

language additions. SystemVerilog-2005 was not a stand-alone language — it was merely a set of

extensions on top of Verilog-2005. One reason for the two documents was to help companies who provide

Verilog simulators and synthesis compilers to focus on implementing all of the new capabilities.

The confusing name change... In 2009, the IEEE merged the Verilog 1364-2005 and the SystemVerilog

extensions (1800-2005) into a single document. For reasons the authors have never understood, the IEEE

chose to stop using the original Verilog name, and changed the name of the merged standard to

SystemVerilog. The original 1364 Verilog standard was terminated, and the IEEE ratified the 1800-2009

SystemVerilog-2009 standard [6] as a complete hardware design and verification language. In the IEEE

nomenclature, there is no longer a current Verilog standard. There is only a SystemVerilog standard. Since

2009, you have not been using Verilog...you have been designing with—and synthesizing—

SystemVerilog! (The IEEE has subsequently released a SystemVerilog-2012 standard, with additional

enhancements to the original, now defunct, Verilog language.)

It is important to note that the SystemVerilog standard extended both the verification and the hardware

modeling capabilities of Verilog. The language growth chart in Figure 1 that follows is not intended to be

comprehensive, but serves to illustrate that a substantial number of the SystemVerilog extensions to the

original Verilog enhance the ability to model hardware. The focus of this paper is on how these constructs

synthesize and the advantages of using these SystemVerilog extensions in hardware design.

SNUG Silicon Valley 2013 5 Synthesizing SystemVerilog

2.1 Value sets

The original Verilog language only had 4-state values, where each bit of a vector could be a logic 0, 1, Z or

X. SystemVerilog added the ability to represent 2-state values, where each bit of a vector can only be 0 or

1. SystemVerilog added the

bit and logic keywords to the Verilog language to represent 2-state and 4-

state value sets, respectively. SystemVerilog net types, such as

wire, only use the logic 4-state value set.

Some variable types use 4-state

logic value sets, while other variables use 2-state bit value sets. (There

is more to the

bit and logic keywords for those that implement simulators and synthesis compilers, but

this generalization suffices for understanding how to model designs using SystemVerilog.)

The

bit and logic keywords can also be used without explicitly defining a net or variable, in which case

a net or variable is inferred from context. The keyword

bit always infers a variable. The keyword logic

infers a variable in most contexts, but infers a net if used in conjunction with a module input or inout

port declaration. The following declarations illustrate these inference rules:

module A;

...

endmodule

module M (

// module ports with inferred types

input i1, // infers a 4-state net

input logic i2, // infers a 4-state net

input bit i3, // infers a 2-state variable

output o1, // infers a 4-state net

output logic o2, // infers a 4-state variable

output bit o3 // infers a 2-state variable

);

// internal signals with inferred and explicit types

bit clock; // infers a 2-state variable

logic reset; // infers a 4-state variable

logic [7:0] data; // infers a 4-state variable

wire [7:0] n1; // explicitly declares a net, infers 4-state logic

wire logic [7:0] n2; // explicitly declares a 4-state net

var [7:0] v1; // explicitly declares a variable, infers logic

var logic [7:0] v2; // explicitly declares a 4-state variable

...

endmodule

Important: Synthesis treats bit and logic the same. 2-state and 4-state value sets are for simulation, and

have no meaning in synthesis.

SystemVerilog Advantage 1 — You no longer need to worry about when to declare modules ports

wire or reg (or, more specifically, a net or a variable). With SystemVerilog, you can declare all

module ports and local signals as

logic, and the language will correctly infer nets or variables for

you (there might be an occasional exception, where an engineer wishes to explicitly use a type

other than what

logic will infer, but those exceptions are rare).

Note that verification code is a little different. In a testbench, randomly generated test values should be

declared as

bit (2-state), rather than logic (4-state). See Sutherland [20] for a detailed exploration of

using 2-state and 4-state types in design and verification code.

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