UWB 芯片DW1000 datasheet

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UWB 芯片DW1000 datasheet 介绍比较详细,适合开发人员
DW1000 Datasheet deca ave List of Figures FIGURE 1: IC BLOCK DIAGRAM FIGURE 22: DW1000SPIPHA=1 TRANSFER PROTOCOL. 21 FiGURE 2: DW1000 PIN ASSIGNMENTS FIGURE 23: SP BYTE FORMATTING 21 FIGURE 3: RX INTERFERER IMMUNITY ON CHANNEL 2. 13 FIGURE 24: SPI CONNECTIONS 22 FiGURE 4 TX outPUt POWER oVER temP VoltagE,, 13 FIGURE 25: DW1000 SPI TIMING DIAGRAM FIGURE 5: RECEIVER SENSITIVITY CHANNEL 5 110K DATA FIGURE 26: DW1000 SPI DETAILED TIMING DIAGRAM.23 RATE 16M PRF 2048 PREAMBLE SYMBOLS 13 FIGURE 27: SYNC SIGNAL TIMING RELATIVE TO XTAL125 FIGURE 6: RECEIVER SENSITIVITY CHANNEL 5 110K DATA FIGURE 28: TYPICAL DEVICE CRYSTAL TRIM PPM RATE 64M PRF 2048 PREAMBLE SYMBOLS 14 ADJUSTMENT,,……4 26 FIGURE 7: RECEIVER SENSITIVITY CHANNEL 5 85OK DATA FIGURE 29: SLEEP OPTIONS BETWEEN OPERATIONS 8 RATE 16M PRF 1024 PREAMBLE SYMBOLS 14 FIGURE 30: TYPICAL RANGE VERSUS TX AVERAGE CURRENT Figure 8: RECEIVER SENSITIVITY CHANNEL 5 8SOK DATA CHANNEL TE64MPRF1024 PREAMBLE SYMBOLS……414 FiGURE 31: TYPICAL TX POWER PROFILE FIGURE 9: RECEIVER SENSITIVITY CHANNEL 56,81M DATA FIGURE 32: TYPICAL RX POWER PROFILE 31 RATE 16M PRF256 PREAMBLE SYMBOLS 15 FIGURE 33: TYPICAL RX POWER PROFILE USING SNIF FIGURE 10 RECEIVER SENSITIVITY CHANNEL 5 6.81M DATA RATE 64M PRF 1256 PREAMBLE SYMBOLS 15 FIGURE 34: POWER SUPPLY CONNECTIONS 32 FIGURE 11: TYPICAL PROBABILITY DISTRIBUTION OF LINE OF FIGURE 35: SWITCHING REGULATOR CONNECTION.3 SIGHT 2-WAY RANGING PERFORMANCE.,15 FIGURE 36: DW1000 APPLICATION CIRCUIT.. 34 FIGURE 12: TX SPECTRUM CHANNEL 1 16 FIGURE 37: PCB LAYER STACK FOR 4-LAYER BOARD ....35 FIGURE 13: TX SPECTRUM CHANNEL 2.m 16 FiGURE 38: DW1000 RF TRACES LAYOUT 36 FIGURE 14: TX SPECTRUM CHANNEL 3 FIGURE 39: DEVICE PACKAGE MECHANICAL SPECIFICATIONS FIGURE 15: TX SPECTRUM CHANNEL 4 …37 FIGURE 16 TX SPECTRUM CHANNEL 5 16 FIGURE 40: DEVICE PACKAGE MARKINGS 38 FIGURE 17 TX SPECTRUM CHANNEL Z....... 16 FIGURE 41: TRAY ORIENTATION ..38 FIGURE 18: IEEE802.15. 4-2011 PPDU STRUCTURE.. 18 FiGURE 42: tape REEl orientation FIGURE 19 IEEE80215. 4-2011 MAC FRAME FORMAT FIGURE 43: TAPE DIMENSIONS L8 FIGURE 44: 330 MM REEL DIMENSIONS .40 FIGURE 20: DW1000 POWER-UP SEQUENCE FIGURE 45: 180 MM REEL DIMENSIONS 40 FIGURE 21: DW1000 SPIPHA=O TRANSFER PROTOCOL 21 List of tables TablE 1: DW1000 PIN FUNCTIONS 6 TablE 15: DW1000 POWER-UP TIMINGS TABLE 2 EXPLANATION OF ABBREVIATIONS 8 TABLE 16: DW1000 SPI MODE CONEIGURATION .......4.22 TAble 3: DW1000 OPERATING CONDITIONS TABLE 17: DW1000 SPI TIMING PARAMETERS 23 TABLE 4: DW1000 DC CHARACTERISTICS 10 TablE 18 tRaNSMIT RECEIVE BUffEr MEmory size. 24 TABLE 5: DWl000 RECEIVER AC CHARACTERISTICS.10 TABLE 19: ACCUMULATOR MEMORY SIZE ..24 TABLE 6: TYPICAL RECEIVER SENSITIVITY CHARACTERISTICS 11 TABLE 20: OTP CALIBRATION MEMORY 24 TABLE DW1000 REFERENCE CLOCK AC CHARACTERISTICS TABLE21: SYNC SIGNAL TIMING RELATIVE TOⅩTAL∴25 TABLE 22: OPERATING STATES Table 8: DW1000 TRANSMITTER AC CHAracteRISTIcs, 12 TABLE 23: OPERATING STATES AND THEIR EFFECT ON POWER Table 9: DW1000 TEMPERATURE AND VOLTAGE MONITOR CONSUMPTION CHARACTERISTICS 12 TABLE 24: OPERATIONAL MODES 28 TABLE 10: DW1000 ABSOLUTE MAXIMUM RATINGS. 12 TABLE 25: TYPICAL TX CURRENT CONSUMPTION 29 TABLE 11: UWB IEEE802.15. 4-2011 UWB CHANNELS TABLE 26: TYPICAL RX CURRENT CONSUMPTION SUPPORTED BY THE DW1000 17 TABle 2/, LOWEST POWER AND LONGEST RANGE MODES OF TABLE 12: UWB IEEE802.15.4-2011 [1]UWB BIT RATES OPERATION 30 AND PRE MODES SUPPORTED BY THE DW1000..17 TABLE28: DEVICE ORDERING| NFORMATION……41 TABLE 13: DW1000 SYMBOL DURATIONS 8 TABLE 29: GLOSSARY OF TERMS TABlE 14: TURN-AROUND TIMES 18 TABlE 30: DOCUMENT HISTORY 43 C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 3 DW1000 Datasheet deca ave DOCUMENT INFORMATION Disclaimer DecaWave reserves the right to change product specifications without notice. As far as possible changes to functionality and specifications will be issued in product specific errata sheets or in new versions of this document. Customers are advised to check with DecaWave for the most recent updates on this product Copyright 2014 DecaWave Ltd LIFE SUPPORT POLICY DecaWave products are not authorized for use in safety-critical applications (such as life support)where a failure of the decaWave product would reasonably be expected to cause severe personal injury or death. DecaWave customers using or selling DecaWave products in such a manner do so entirely at their own risk and agree to fully indemnify DecaWave and its representatives against any damages arising out of the use of DecaWave products in such safety-critical applications Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage REGULATORY APPROVALS The DW1000, as supplied from DecaWave, has not been certified for use in any particular geographic region by the appropriate regulatory body governing radio emissions in that region although it is capable of such certification depending on the region and the manner in which it is used All products developed by the user incorporating the dw 1000 must be approved by the relevant authority governing radio emissions in any given jurisdiction prior to the marketing or sale of such products in that urisdiction and user bears all responsibility for obtaining such approval as needed from the appropriate authorities C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 4 DW1000 Datasheet deca ave IC DESCRIPTION DIGITAL RI Cigital Filte Bascba and Diagnostics Configuration Host Interface Imers Gain Control Reg ster Digital AON . 6I VDDPAl blocks via PMsc Convolutional SECDED Transmit Ene。der RF TX DIGTAL TX circuits AON VDnAON DIGITAL Control Tx/ Rx RF PLL I Synth IFMSC VDDLDOD CLK PLL/Synth Figure 1: IC Block Diagram DW1000 is a fully integrated low-power, single chip initial frequency error adjustment, and range CMOS RF transceiver Ic compliant with the accuracy adjustment. These adjustment values can IEEE802.15.4-2011 [1]UWB standard be automatically retrieved when needed. See section 5. 14 for more details DW1000 consists of an analog front end containing a receiver and a transmitter and a digital back end The Always-On (AON) memory can be used to that interfaces to an off-chip host processor. A retain DW1000 configuration data during the lowest TX/RX switch is used to connect the receiver or power operational states when the on-chip voltage transmitter to the antenna port. Temperature and regulators are disabled This data is uploaded and voltage monitors are provided on-chip downloaded automatically. Use of DW1000 AON memory is configurable The receiver consists of an rf front end which amplifies the received signal in a low-noise amplifier The DW1000 clocking scheme is based around 3 before down-converting it directly to baseband. the main circuits, Crystal Oscillator, Clock PLL and RF receiver is optimized for wide bandwidth, linearity PLL. The on-chip oscillator is designed to operate and noise figure. This allows each of the supported at a frequency of 38. 4 MHz using an external IEEE802. 15. 4-2011 1 UWB channels to be down crystal. An external 38. 4 MHz clock signal may be converted with minimum additional noise and applied in place of the crystal if an appropriately distortion. The baseband signal is demodulated stable clock is available elsewhere in the users system. This 38. 4 MHz clock is used as the and the resulting received data is made available to the host controller via sp reference clock input to the two on-chip PLLs. The clock PLL (denoted CLKPLL) generates the clock The transmit pulse train is generated by applying equired by the digital back end for signal digitally encoded transmit data to the analog pulse processing The RF PLL generates the down- generator. The pulse train is up-converted by a conversion local oscillator(LO) for the receive chain double balanced mixer to a carrier generated by the and the up-conversion Lo for the transmit chain synthesizer and centered on one of the permitted An internal 13 kHz oscillator is provided for use in the sleep state IEEE802.15. 4-2011 [1 UWB channels. The modulated RF waveform is amplified before The host interface includes a slave-only sPI for transmission from the external antenna device communications and configuration. A The IC has an on-chip One-Time Programmable number of MAC features are implemented including (OTP)memory. This memory can be used to store CRC generation, CRC checking and receive frame calibration data such as TX power level, crystal filtering C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 5 DW1000 Datasheet deca ave 2 PIN CONNECTIONS 2.1 Pin Numbering QFN-48 package with pin assignments as follows Viewed from to Mark 守守导好寸守于导男85 NC1口 □36GP|O2/ RXLED NC 2 35 GPIO3/ TXLED EXTCLK/XTAL13□ [34 GPIO4/EXTPA XTAL24□ □49GND [33 GPIO5/EXTTXE/SPIPHA F5□ 口32ss|C VDDIF 7 30 GPIO6EXTRXE/ SPIPOL CLKTUNE 8口 □29sYNc/GPO7 VDDCLK9口 口28 VDDIOA VDDSYN10□ 日27RsTn □26 DDLDOD COTUNE 12 25 VDDAON g*= 92888t 2乏a2出3员 Figure 2: DW1000 Pin Assignments 2.2 Pin Descriptions Table 1: DW1000 Pin functions SIGNAL NAME PIN DESCRIPTION (default) Crystal Interface EXTCLK/XTAL13 A Reference crystal input or external reference overdrive pin XTAL2 4 Al Reference crystal input Digital Interface SPICLK 41 D SPI clock DO SPIMISO 40 (O-L) SPl data output. Refer to section 5.8 SPIMOSI 39 SPl data input. Refer to section 5.8. SPl chip select. This is an active low enable input. The high-to-low SPICSn 24 transition on SPICSn signals the start of a new SPI transaction. SPICSr can also act as a wake-up signal to bring dW1000 out of either SLEEP or DEEPSLEEP states. Refer to section 6 SYNC/GPIO7 29 DIo The SYNC input pin is used for external synchronization(see section be reconfigured as a general purpose l/O pin, GPlO used this pin may 5. 13). When the SYNC input functionality is not being WAKEUP 23 When asserted into its active high state, the WaKeuP pin brings the DW1000 out of SLEEP or DEEPSLEEP states into operational mode C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 6 DW1000 Datasheet deca ave SIGNAL NAME PIN DESCRIPTION (default) EXternal device enable. Asserted during wake up process and held active DO until device enters sleep mode. Can be used to control external DC-DC EXTON 21(0-L) sleep mode so as to minimize power consumption Refer to sections 5.5.1 converters or other circuits that are not required when the device is in 87. FORCEON 22 D Not used in normal operation. Must be connected to ground Interrupt Request output from the dW1000 to the host processor. By default IRQ is an active-high output but may be configured to be active low if required. For correct operation in SLEEP and DEEPSLEEP modes IRQ /GPIO8 45 Dio it should be configured for active high operation. This pin will float in (O-L) SLEEP and DEEPSLEEP states and may cause spurious interrupts unless pulled low When the iRQ functionality is not being used the pin may be reconfigured as a general purpose l70 line, GPIO8 General purpose l/0 pin On power-up it acts as the sPIPOL (SPl polarity selection) pin for GPIO6/ EXTRXE DIO configuring the SPl operation mode. For details of this please refer to section 5. 8 SPIPOL After power-up, the pin will default to a General Purpose l /o pin It may be configured for use as EXTRXE (External Receiver Enable). This pin goes high when the dW1000 is in receive mode General purpose 1/0 pin On power-up it acts as the SP IPHA (SPl phase selection) pin for GPIO5/EXTTXE33 Dio configuring the SPI mode of operation. Refer to section 5. 8 for further information SPIPHA After power-up, the pin will default to a General Purpose l/o pin It may be configured for use as EXTTXE(External Transmit Enable). This pin goes high when the DW1000 is in transmit mode DIO General 0 pin GPIO4/EXTPA 34 () It may be configured for use as EXTPA (External Power Amplifier).This pin can enable an external Power Amplifier. General purpose l /o pin DIO GPIO3/TXLED It may be configured for use as a TXLED driving pin that can be used to (I light a LED following a transmission. Refer to the DW1000 User Manual 2] for details of LEd use General purpose l/o pin GPIO2/RXLED36 Dio It may be configured for use as a rXLED driving pin that can be used to (0) light a LED during receive mode. Refer to the DW1000 User Manual [2] for details of led use General purpose l/o pin GPIO1/SFDLED37 DIo It may be configured for use as a SFDLED driving pin that can be used to () light a LED when SFD (Start Frame Delimiter) is found by the receiver Refer to the DW1000 User Manual [2] for details of LEd use General purpose i/o pin GPIO0 DIO 38 lt be configured for use as a rXoKled driving pin that can be used RXOKLED (0) to light a LED on reception of a good frame. Refer to the DW1000 User Manual [2] for details of LEd use DIO Reset pin Active Low Output RSTn 27 (O-H) May be pulled low by external open drain driver to reset the DW1000 Must not be pulled high by external source. Refer to section 5.6 TESTMODE 46 D Not used in normal operation must be connected to ground Reference voltages VREF AIO Used for on-chip reference current generation Must be connected to an 11 kQ(1% tolerance)resistor to ground Digital Power Supplies VDDLDOD 26 I P External supply for digital circuits. C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 7 DW1000 Datasheet deca ave SIGNAL NAME PIN(default) DESCRIPTION VDDIOA 28 P External supply for digital Io ring. 32 G 43 Negative 1/0 ring supply Must be connected to ground Digital Decoupling VDDREG 20 PD Output of on-chip regulator. Connect to VDDDIG on PCB VDDDIG 44 PD Output of on-chip regulator. Connect to VDDREG on PCB 31 VDDIO 42 PD Digital IO Ring Decoupling RF Interface RE P 16 AIO Positive pin of the 100 n differential RF pair. Should be AC coupled. RE N 17 AIO Negative pin of the 100 12 differential RF pair Should be AC coupled PLL Interface CLKTUNE Alo Clock PLL loop filter connection to off-chip filter components. Referenced to VddcLK VCOTUNE 12 AlO RF PLL loop filter connection to off-chip filter components Referenced to VDDVCO Analog Power Supplies VDDAON EXternal supply for the Always-On(AON) portion of the chip. See 7.3 VDDPA1 18 PPP External supply to the transmitter power amplifier VDDPAZ 19 External supply to the transmitter power amplifier. VDDLNA P External supply to the receiver LNA VDDLDOA P External supply to analog circuits /DDBATT 47 External supply to all other on-chip circuits Analog Supply Decoupling VDDCLK PD VDDIF 976 Output of on-chip regulator to off-chip decoupling capacitor Output of on-chip regulator to off-chip decoupling capacitor. VDDMS PD Output of on-chip regulator to off-chip decoupling capacitor. VDDSYN PD Output of on-chip regulator to off-chip decoupling capacitor VDDVCO Output of on-chip regulator to off-chip decoupling capacitor Ground Paddle GND 49 Ground Paddle on underside of package. Must be soldered to the PCB ground plane for thermal and rf performance Others 2 NC NC Not used in normal operation do not connect 13 Table 2: Explanation of Abbreviations ABBREVIATION EXPLANATION Analog Input AlO Analog Input/Output AO Analog Output Digital Input DIO Digital Input/ Output DO Digital Output GRound C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 8 DW1000 Datasheet deca ave ABBREVIATION EXPLANATION Power Supply PD Power Decoupling NC No Connect Defaults to output, low level after reset O-H Defaults to output, high level after reset Defaults to input Note: Any signal with the suffix n'indicates an active /ow signal C DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 9 DW1000 Datasheet deca ave 3 ELECTRICAL SPECIFICATIONS 3. 1 Nominal Operating Conditions Table 3: DW1000 Operating Conditions Parameter M Typ. Max. Units Condition/Note Operating temperature 40 C Supply voltage VDDIOA 3.3 3.6 Supply voltage VDDBATT, VDDAON VDDLNA. VDDPA 3.3 3.6 Supply voltage VDDLDOA, VDDLDOD 1.6 3.6 See section 7.2 Only to if programming Optional: Supply voltage VDDIO 3.7 3.8 3.9 the OTP memory. See the DW1000 User Manual [2]for details Note: Unit operation is guaranteed by design when operating within these ranges 3.2 DC Characteristics Tamb= 25'C, all supplies centered on typical values Table 4: dW1000 DC Characteristics Parameter Min Typ Max Units Condition/Note Supply current DEEP SLEEP mode 50 nA Supply current SLEEP mode A Total current drawn from al Supply current IDLE mode 3.3V and 1.8 V supplies Supply current INIT mode 4 TX :3.3 V supplies VDDBAT VDDPA1. VDDPA2, VDDLNA anne VDDAON, VDDIOAI TX Power MAX mean TX 1.8 V supplies 90 ma-9. dBm/500 MHz) ∨ DDLDOA, VDDLDOD RX 33V supplies OVDDBAT, VDDPA1, VDDPA2, VDDLNA 30 mA VDDAON. VDDIOA Channel 5 RX 18V supplies 210* mA (VDDLDOA, VDDLDOD) Digital input voltage high 0*VDDIO V Digital input voltage low 0.3VDDIO Digital output voltage high 0.7VDDIO Assumes 500 Q load Digital output voltage low 0. 3*VDDIO Assumes 500 Q load Digital Output Drive Current GPIOX, IRQ SPIMISO 8 EⅩToN 4 These currents are on the 1. 8V supplies, not referenced back to the 3.3 V supply 3. 3 Receiver AC Characteristics Tamb=25'C, all supplies centered on nominal values Table 5: dw1000 Receiver Ac characteristics Parameter Min Max.Units Condition/Note Frequency range 3244 6999 MHZ 500 Channel 1.2.3 and 5 Channel bandwidths MHz 900 Channel 4 and 7 c DecaWave ltd 2014 Subject to change without notice Version 2.04 Page 10

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