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TMS320VC5502用户手册
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TMS320VC5502
Fixed-Point Digital Signal Processor
Data Manual
Literature Number: SPRS166J
April 2001 – Revised August 2006
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Revision History
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
This data sheet revision history highlights the technical changes made to the SPRS166I device-specific
data sheet to make it an SPRS166J revision.
Scope: Updated parametric value, etc.
ADDITIONS/CHANGES/DELETIONS
Table 3-60 , Instruction Cache Registers:
• ICWMC:
– changed WORD ADDRESS from 0x1403 to 0x1409
– changed DESCRIPTION from "ICache N-Way Control Register" to "ICache Way Miss-Counter Register"
Table 3-77 , Interrupt Table:
• Priority 17:
– changed NAME from "RINT2" to "RINT2/UART"
– changed FUNCTION from "McBSP #2 receive interrupt" to "McBSP #2 transmit interrupt or UART interrupt"
Figure 5-23 , External Interrupt Timings:
• updated figure to show that signals transition from high to low
Table 5-32 , McBSP Transmit and Receive Switching Characteristics:
• M5 [t
d(CKXH-FXV)
, CLKX int ]: changed MIN value from –2 ns to 0 ns
2 Revision History Submit Documentation Feedback
www.ti.com
Contents
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
Revision History ........................................................................................................................... 2
1 TMS320VC5502 ................................................................................................................. 13
1.1 Features ..................................................................................................................... 13
2 Introduction ....................................................................................................................... 14
2.1 Description .................................................................................................................. 14
2.2 Pin Assignments ............................................................................................................ 15
2.2.1 Ball Grid Array (GZZ and ZZZ) ................................................................................ 15
2.2.2 Low-Profile Quad Flatpack (PGF) ............................................................................. 17
2.2.3 Signal Descriptions .............................................................................................. 19
3 Functional Overview ........................................................................................................... 31
3.1 Memory ...................................................................................................................... 32
3.1.1 On-Chip ROM ................................................................................................... 32
3.1.2 On-Chip Dual-Access RAM (DARAM) ........................................................................ 33
3.1.3 Instruction Cache ................................................................................................ 33
3.1.4 Memory Map ..................................................................................................... 34
3.1.5 Boot Configuration ............................................................................................... 35
3.2 Peripherals .................................................................................................................. 35
3.3 Configurable External Ports and Signals ................................................................................ 36
3.3.1 Parallel Port Mux ................................................................................................ 36
3.3.2 Host Port Mux .................................................................................................... 37
3.3.3 Serial Port 2 Mux ................................................................................................ 38
3.3.4 External Bus Selection Register (XBSR) ..................................................................... 39
3.4 Configuration Examples ................................................................................................... 41
3.5 Timers ........................................................................................................................ 42
3.5.1 Timer Interrupts .................................................................................................. 43
3.5.2 Timer Pins ........................................................................................................ 44
3.5.3 Timer Signal Selection Register (TSSR) ..................................................................... 45
3.6 Universal Asynchronous Receiver/Transmitter (UART) ............................................................... 46
3.7 Inter-Integrated Circuit (I
2
C) Module ..................................................................................... 48
3.8 Host-Port Interface (HPI) .................................................................................................. 49
3.9 Direct Memory Access (DMA) Controller ................................................................................ 50
3.9.1 DMA Channel 0 Control Register (DMA_CCR0) ........................................................... 50
3.10 System Clock Generator .................................................................................................. 52
3.10.1 Input Clock Source .............................................................................................. 53
3.10.2 Clock Groups ..................................................................................................... 55
3.10.3 EMIF Input Clock Selection .................................................................................... 56
3.10.4 Changing the Clock Group Frequencies ..................................................................... 56
3.10.5 PLL Control Registers .......................................................................................... 58
3.10.6 Reset Sequence ................................................................................................. 69
3.11 Idle Control .................................................................................................................. 69
3.11.1 Clock Domains ................................................................................................... 70
3.11.2 IDLE Procedures ................................................................................................ 70
3.11.3 Module Behavior at Entering IDLE State ..................................................................... 72
3.11.4 Wake-Up Procedure ............................................................................................ 73
3.11.5 Auto-Wakeup/Idle Function for McBSP and DMA ........................................................... 75
3.11.6 Clock State of Multiplexed Modules ........................................................................... 75
3.11.7 IDLE Control and Status Registers ............................................................................ 76
3.12 General-Purpose I/O (GPIO) ............................................................................................. 84
3.12.1 General-Purpose I/O Port ...................................................................................... 84
3.12.2 Parallel Port General-Purpose I/O (PGPIO) ................................................................. 86
Contents 3
www.ti.com
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
3.13 External Bus Control Register ............................................................................................ 96
3.13.1 External Bus Control Register (XBCR) ....................................................................... 97
3.14 Internal Ports and System Registers .................................................................................... 98
3.14.1 XPORT Interface ................................................................................................ 98
3.14.2 DPORT Interface ............................................................................................... 100
3.14.3 IPORT Interface ................................................................................................ 102
3.14.4 System Configuration Register (CONFIG) .................................................................. 103
3.14.5 Time-Out Control Register (TOCR) .......................................................................... 104
3.15 CPU Memory-Mapped Registers ....................................................................................... 105
3.16 Peripheral Registers ...................................................................................................... 107
3.17 Interrupts ................................................................................................................... 120
3.17.1 IFR and IER Registers ....................................................................................... 121
3.17.2 Interrupt Timing ................................................................................................ 122
3.17.3 Interrupt Acknowledge ......................................................................................... 122
3.18 Notice Concerning TCK .................................................................................................. 123
4 Support ........................................................................................................................... 125
4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability ....................................... 125
4.1.1 Initialization Requirements for Boundary Scan Test ...................................................... 125
4.1.2 Boundary Scan Description Language (BSDL) Model .................................................... 125
4.2 Documentation Support .................................................................................................. 125
4.3 Device and Development-Support Tool Nomenclature .............................................................. 127
5 Specifications .................................................................................................................. 128
5.1 Electrical Specifications .................................................................................................. 128
5.2 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 128
5.3 Recommended Operating Conditions .................................................................................. 128
5.4 Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 129
5.5 Timing Parameter Symbology ........................................................................................... 130
5.6 Clock Options ............................................................................................................. 131
5.6.1 Internal System Oscillator With External Crystal ........................................................... 131
5.6.2 Layout Considerations ......................................................................................... 132
5.6.3 Clock Generation in Bypass Mode (APLL Disabled) ...................................................... 133
5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled) ............................................. 134
5.6.5 EMIF Clock Options ........................................................................................... 135
5.7 Memory Timings .......................................................................................................... 137
5.7.1 Asynchronous Memory Timings .............................................................................. 137
5.7.2 Programmable Synchronous Interface Timings ........................................................... 140
5.7.3 Synchronous DRAM Timings ................................................................................. 143
5.8 HOLD/ HOLDA Timings .................................................................................................. 148
5.9 Reset Timings ............................................................................................................. 149
5.10 External Interrupt and Interrupt Acknowledge ( IACK) Timings ..................................................... 151
5.11 XF Timings ................................................................................................................. 152
5.12 General-Purpose Input/Output (GPIOx) Timings ..................................................................... 153
5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings .......................................................... 154
5.14 TIM0/TIM1/WDTOUT Timings .......................................................................................... 155
5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings ................................................................... 155
5.14.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings ...................................................... 156
5.14.3 TIM0/TIM1/WDTOUT Interrupt Timings ..................................................................... 158
5.15 Multichannel Buffered Serial Port (McBSP) Timings ................................................................. 159
5.15.1 McBSP Transmit and Receive Timings ..................................................................... 159
5.15.2 McBSP General-Purpose I/O Timings ...................................................................... 162
5.15.3 McBSP as SPI Master or Slave Timings .................................................................... 163
Contents 4 Submit Documentation Feedback
www.ti.com
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
5.16 Host-Port Interface Timings ............................................................................................. 170
5.16.1 HPI Read and Write Timings ................................................................................. 170
5.16.2 HPI General-Purpose I/O Timings ........................................................................... 177
5.16.3 HPI. HAS Interrupt Timings .................................................................................... 179
5.17 Inter-Integrated Circuit (I
2
C) Timings ................................................................................... 180
5.18 Universal Asynchronous Receiver/Transmitter (UART) Timings ................................................... 182
6 Mechanical Data ............................................................................................................... 183
6.1 Package Thermal Resistance Characteristics ........................................................................ 183
6.2 Packaging Information ................................................................................................... 184
Contents 5
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