Contents
1. JESD204B IP Quick Reference.........................................................................................4
2. About the JESD204B Intel FPGA IP................................................................................. 6
2.1. Release Information...............................................................................................8
2.2. Device Family Support............................................................................................8
2.3. Datapath Modes.................................................................................................... 9
2.4. IP Variation...........................................................................................................9
2.5. JESD204B IP Configuration....................................................................................10
2.5.1. Run-Time Configuration............................................................................ 11
2.6. Channel Bonding..................................................................................................12
2.7. Performance and Resource Utilization..................................................................... 14
3. Getting Started............................................................................................................. 20
3.1. Introduction to Intel FPGA IP Cores........................................................................ 20
3.2. Installing and Licensing Intel FPGA IP Cores............................................................ 21
3.3. Intel FPGA IP Evaluation Mode...............................................................................22
3.4. Upgrading IP Cores.............................................................................................. 24
3.5. IP Catalog and Parameter Editor............................................................................ 28
3.6. Design Walkthrough............................................................................................. 28
3.6.1. Creating a New Intel Quartus Prime Project................................................. 28
3.6.2. Parameterizing and Generating the IP.........................................................29
3.6.3. Compiling the JESD204B IP Core Design..................................................... 30
3.6.4. Programming an FPGA Device....................................................................31
3.7. JESD204B Design Examples.................................................................................. 31
3.8. JESD204B IP Design Considerations....................................................................... 31
3.8.1. Integrating the JESD204B IP in Platform Designer........................................ 31
3.8.2. Pin Assignments...................................................................................... 33
3.8.3. Adding External Transceiver PLLs............................................................... 33
3.8.4. Timing Constraints For Input Clocks............................................................33
3.9. JESD204B Intel FPGA IP Parameters.......................................................................36
3.10. JESD204B IP Component Files............................................................................. 41
3.11. JESD204B IP Testbench...................................................................................... 41
3.11.1. Generating and Simulating the IP Testbench.............................................. 42
3.11.2. Testbench Simulation Flow.......................................................................45
4. JESD204B IP Functional Description............................................................................ 46
4.1. Transmitter......................................................................................................... 48
4.1.1. TX Data Link Layer...................................................................................49
4.1.2. TX PHY Layer.......................................................................................... 52
4.2. Receiver............................................................................................................. 52
4.2.1. RX Data Link Layer...................................................................................53
4.2.2. RX PHY Layer.......................................................................................... 56
4.3. Operation........................................................................................................... 56
4.3.1. Operating Modes......................................................................................57
4.3.2. Scrambler/Descrambler............................................................................ 59
4.3.3. SYNC_N Signal........................................................................................ 60
4.3.4. Link Reinitialization.................................................................................. 61
4.3.5. Link Startup Sequence..............................................................................62
Contents
JESD204B Intel
®
FPGA IP User Guide
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