TTL CMOS PECL LVPECL LVDS HCSL信号电平及阻抗匹配标准.pdf

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TTL CMOS PECL LVPECL LVDS HCSL信号电平及阻抗匹配标准,详细描述了以上的各种电平标准
Application Note supply and at one time had higher transmit speeds compared to CMOS, up to 100 MHZ. Also it was more popular since power consumption didn't change as drastically with higher output frequencies ttl outputs can also be dealt with using methods described for CMOS signals. During the 1980s CMoS devices became more popular, particularly for large scale integration because of their low(zero)quiescent current, good noise immunity, improved rise/fall times and lower cost of manufacture. CMOS has displaced TtL as the preferred choice for low frequency clocking ICs The primary benefits of CMOS and TtL are low power consumption, higher output swing, and relatively low cost implementation in silicon. However, differential signals are used for higher frequencies Differential Logic Families Single ended signal transmission techniques can be susceptible to noise. This can be overcome by increasing the voltage, but this increases the power consumption and results in lower speeds due to the voltage swing. Single ended transmission lines also tend to attenuate the signal; again this can be overcome by increasing the transmission voltage. Differential buffers overcome these difficulties by transmitting a pair of complementary signals (opposite polarities)for every bit sent. The receiver detects differences between the two signals and any noise common to both signals is rejected. Differential transmission techniques are influenced less by line attenuation because of their greater noise immunity and because of this are ideal for transmitting at higher data rates over longer line lengths. ECL (single ended or differential) Emitter Coupled Logic(ECL) was introduced as an alternative to Ttl logic because it is better suited for high speed data transmission Emitter-Coupled Logic circuits use transistors to steer current through gates which compute logical functions Because the transistors are always in the active region, they can change state very rapidly, So ECL circuits can operate at very high speeds ECL suffers from two disadvantages. First, ECL requires relatively high currents to operate. Secondly, ECL relies on a negative power supply for operation This can cause problems when interfacing to positive-supply-based devices residing in the rest of the system. But being referenced to ground, could offer noise advantages PECL LVPECL LVPECL and PECl are both offshoots of the older ecl technology first introduced in the 1960s PECl stands for Positive Emitter Coupled logic as it operates off a positive voltage such as 5, 3.3V or 2.5V. PECL logic outputs are commonly used in high-speed clock distribution circuits. As a differential transmission scheme PECL has the advantage of high noise immunity and the ability to drive high data rates over long line lengths. Another advantage of PECl includes good jitter performance due to the large voltage swing. Disadvantages include large power consumption(compared to a single ended supply) due to the need for a 5v supply and external DC biasing Low Voltage PECL (LVPECL)refers to PECL circuits designed for use with 3. 3V or 2.5V supply, the same supply voltages as for low voltage CmoS devices. LVPECL forms the basis of a number of protocols including Gigabit Ethernet and Fibre channel. The LVPECL electrical specification is similar to LVDS, but operates with a larger differential voltage swing LVPECL tends to be a little less power efficient than lvdS due to its ECl origins and larger swings, however it can also operate at frequencies up to 10 Gbps because of its ecl characteristics LVPECL output currents are typically 15mA, and this is derived from an open emitter. This requires termination into a resistive load to produce a voltage. The intent for LVPECL is to use a 50 ohm impedance trace and 50 ohm thevinen equivalent load. This is usually implemented using figure 5 and an alternative scheme is shown in figure 6. For best performance, the outputs should be equally terminated using the same method -an unused output should never be left floating. Also differential receivers from different manufacturers can have different input tolerances (while still clustered around a common standard). Doing some homework on the requirements of the receiver can also help to optimize the transmission of the signal you are looking to terminate VectronInternational-267LowellRoadHudsonNh03051.tel:1-88-vectron-1.Http://www.vectron.com Page 3 Application Note 3.3V +3.3V 33V +33V R11250 R1125Q z0509 LVPECL> LVPEC LVFEC z0509 LVPEC z0509 R2423R2049 500 50Q 50g Figure 5. The most common approach to LVPECL Figure 6. An alternative LVPECL termination scheme termination CML Current-Mode Logic(CML)outputs provide similar performance to LVPECL but do not require an external bias and so Cml is an option when an LVPECL type output is required but power consumption is a concern Cml outputs need to be ac-coupled since they cannot provide sufficient current to bias other devices LVDS LVDS Stands for Low Voltage Differential Signaling, and is similar to LVPECL being a current output, however the output current is 4mA which results in lower power consumption compared to LVPECL LVDS outputs have a 100 ohm output impedance and is meant to drive a 100 ohm load or resistor, this results in smaller voltage swings ty pically -350mV LVDS maintains reduced susceptibility to noise, lower EMI emissions compared to Cmos and TTL. a disadvantage of lvDS can be its reduced jitter performance compared to PECL; however advances are being made putting it on a level playing feld with LVPECL LVDS is used in high speed data transfer applications, in particular backplane transceivers or clock distribution. LVDS operates at data rates up to 3. 125 Gbps. For higher data rates, outputs such as HCSL, CML or LVPECL are required. Achieving these very high data rates requires very fast, sharp-edge rates and typically a signal swing of approximately 800 mV. Because of this HCSL, CML and LvPECL generally require more power than LVDS LVDS is typically chosen for newer designs because of its ease of implementation in CMoS ICs and because of ease of use at the system level. LVDS outputs require no external biasing and a single 100 ohm termination resistor when connected to lvds inputs, see figure 7. The LVDS signal may or may not need to be ac coupled after the 100 ohm load-it's always best to understand the recievers input structure requirements +3.3V 3.3V LVDS 100QLVDS Figure 7. Terminating LVDS. Often the receiver includes on chip termination and the additional 100 ohm resistor is not required HCSL High Speed Current Steering Logic(HCSL)outputs are found in PCI express applications and Intel chipsets. HCSL is a newer dif- VectronInternational-267LowellRoadHudsonNh03051.tel:1-88-vectron-1.Http://www.vectron.com age 4 Application Note ferential output standard, similar to LVPECL, with a 15mA current source being derived from an open emitter or source. Being un-terminated drains, they require external 50 ohm resistors to ground as shown in in figure 8. HCSL is a high impedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 9, to help reduce overshoot/ringing. HCSL provides the quickest switching speeds, power consumption is between LVDS and LVPECL, and phase noise performance compares well with the alternative technologies. As always it is best practice to understand a receivers input structure +3.3V +3.3V∨ Z0509 10-309 Z0509 HCSL HCSL 10-309 Z050g z0509 509 50Q 50 50 Figure 8. Single Resistor Termination Scheme Figure 9. In some cases a 10-30 ohm series resistor is used to help reduce overshoot. Page VectronInternational-267LowellrOad,HudsonNh03051.Tel:1-88-vectron-1.hTtp://www.vectron.com Application Note Benefits/Tradeoffs Jitter. LVPECL can offer best jitter performance followed by LVDS, and then CMOS; however CMOS can usually provide better phase noise albeit slower rise and fall times resulting in degraded jitter in some cases Power For the best power consumption use CMOS or LVDS LVPECL is faster but consumes more power Speed HCSL and LVPECL is faster but can consume more power. LVDS is faster than CMOS Single ended Vs differential Differential signals are resistant to common mode noise which single ended techniques are susceptible to, and there are less EMI concerns. Additionally, differential signals have better rise and fall time. However, sinewave generally offers the best phase noise followed by Cmos then differential Ease of use LVPECL requires external resistors for termination at both transmitter and receiver ends. LVDS requires only single resistor at receiver For Additional Information Please Contact USA Europe: Asia Vectron International Vectron International Vectron Internationa Hudson, NH 03051102 267 Lowell road, Unit Landstrasse, D-74924 68 Yin Cheng road(c), 22nd Floor Neckarbischofsheim, Germany One lujiazui Tel:1.888328.7661 Te:+49(0)72688010 Pudong, Shanghai 200120, China Fax:1.888.329.8328 Fax:+49(0)7268801281 Te:86.21.61946886 Fax:8621.61633598 Disclaimer Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application No rights under any patent accompany the sale of any such product(s)or information VectronInternational-267LowellrOad,HudsonNh03051.Tel:1-88-vectron-1.hTtp://www.vectron.com Page 6

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