cyclone3-用户手册

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cyclone3-用户数据手册,以及该芯片的功能实现
A A Chapter Revision Dates Chapter 1. Cyclone ili device Family overview R evise March 2007 Part number: CII51001-10 Chapter 2. Logic Elements and Logic Array Blocks in Cyclone Ill Devices Revised March 2007 Part number: CI1151002-10 Chapter 3. Multitrack Interconnect in Cyclone lll Devices Revised March 2007 Part number: CIlI51003-10 Chapter 4. Memory Blocks in Cyclone Ill Devices Revised March 2007 Part number: CIl151004-10 Chapter 5. embedded Multipliers in Cyclone ill devices Revised March 2007 Part number: CIII51005-10 Chapter 6. Clock Networks and PLLs in Cyclone Ill Devices Revised March 2007 Part number: CII151006-10 Chapter 7. Cyclone Ill Device I/O Features Revised March 2007 Part number: Cl1151007-10 Chapter8. High-Speed Differential Interfaces in Cyclone Ill Devices Revised March 2007 Part number: CII51008-10 Chapter 9. External memory Interfaces in Cyclone Ill Devices Revised March 2007 Part number: C/151009-10 Chapter 10. Configuring Cyclone Ill devices Revised March 200 Part number: CI1I51010-10 Altera Corporation i Chapter Revision Dates Cyclone Ill Device Handbook, Volume 1 Chapter 11. Hot Socketing and Power-On Reset in Cyclone Ill devices R evise March 2007 Part number: CIII51011-10 Chapter 12. Remote System Upgrade With Cyclone Ill Devices Revised March 2007 Part number: CI1151012-10 Chapter 13. SEU Mitigation in Cyclone Ill Devices Revised March 200 Part number: CIII51013-10 Chapter 14. IEEE 1149.1 TAG)Boundary-Scan Testing for Cyclone IlI Devices Revised March 2007 Part number: CI51014-10 Chapter 15. Package Information for Cyclone iii Devices Revised March 2007 Part number: CI51015-10 Altera Corporation AALBRA Contents Chapter Revision Dates About this handbook :a::::aa.:aa:::na::: How to Contact altera Typographic Conventions…… X111 Section Device Core Chapter 1. Cyclone I Device Family Overview Cyclone Il: Lowest System-Cost FPGas Features…… Reduced Cost Lowest-Power 65-nm Fpga Increased System Integration ·,, Cyclone Ill device architecture LEs and labs Multitrack interconnect Memory block Embedded Multipliers and Digital Signal Processing Support I/O Features......... Clock Networks and plls High-Speed Differential Interfaces…… 1-10 Auto-Calibrating External Memory Interfaces .1-10 Quartus II Software Support Nios ii- the Worlds most versatile embedded processor 1-11 Configuration…… Remote System Upgrades 1-12 Hot Socketing and Power-On-Reset SEU Mitigation…… ……1-13 TAG Boundary Scan Testing……………… Reference and Ordering Information .1-13 Document revision history. ................................................................................................1-14 Chapter 2. Logic Elements and Logic Array Blocks in Cyclone Ill Devices Introduction ‘‘“··‘+‘“·‘““ Logic elements LE Features∴ Altera Corporation Contents Cyclone Ill Device Handbook, Volume 1 LE Operating modes… Logic array blocks……… LAB Interconnects LAB Control signals… Conclusion 2-11 Document revision history......... 2-11 Chapter 3. MultiTrack Interconnect in Cyclone Ill Devices Introduction Multitrack interconnect 3-1 Row Interconnects Column interconnects Device routing LAB Local Interconnects M9 K Routing Interface……… Embedded Multiplier routing Interface 3-10 Conclusion .....,3-11 Document revision historv Chapter 4. Memory blocks in Cyclone I Devices Introduction verveⅴ Control signals…… Parity Bit Support…… 4-4 Byte Enable Support……………… 4-4 Packed Mode Support…… 4-6 Address Clock Enable Support…… Mixed Width Support……… Asynchronous Clear Memory modes…… 4-10 Single-port mode 4-10 Simple dual-port Mode :·“‘“·····:· 412 rue Dua Dae Shift register Mode……… ∴4-15 ROM Mode 4-17 FIFO Buffer mode 4-17 Clocking modes 4-17 Independent Clock Mode 4-18 Input/ Output Clock mode 4-20 Read/ write Clock mode Single-Clock mode 4-25 Design Considerations.... Read-During-Write Operations .... 4-28 Conflict Resolution 4-31 Power-Up Conditions and Memory Initialization 4-32 Power Management… 4-32 Altera Corporation Contents Document revision history Chapter 5. Embedded Multipliers in Cyclone Ill Devices Embedded Multiplier block overview Architecture Multiplier Stage…… Output registers 5-7 18-Bit Multipliers..... 9- Bit multipliers… 5-8 Software Support 5-10 Document revision history Chapter 6. clock Networks and Plls in cyclone Ill Devices Introducti Clock networks Global Clock Network Clock Control block ..........................................................................6-6 Global Clock network Clock source generation Global Clock Network power Down Clkena signals PLLs in Cyclone Ill devices Cyclone III PLL………… 6-16 Cyclone III PLL Hardware Overview 6-16 Cyclone Ill PLL Software Overview ..6-19 Clock Feedback modes 6-21 Source-Synchronous mod No Compensation Mode √ ormal mode ·‘:··:·‘…· 6-23 Zero delay Buffer(zDB) Mode Hardware Features…… 24 Clock Multiplication and division ...... 6-24 Post-scale Counter Cascading Programmable duty cycle PLL Control signals 6-26 Clock switchover Manual override Phase-Shift Implementation…… PLL Cascading PLL Reconfiguration . 37 PLL Reconfiguration Hardware Implementation pread-Spectrum Clocking 6-47 PLL Specifications Altera Corporation Contents Cyclone Ill Device Handbook, Volume 1 Board Layout VCCA and gnDa VCCD and GND 648 -49 Document revision history Section I 1/0 and External Memory Interfaces Chapter 7. cyclone I Device /0 Features Introducti Overview… Cyclone Ill I/O Element Features...... Programmable Current strength 7-8 Slew rate contr 7-11 Open-Drain Output… 7-11 Bus hold Programmable pull-up resistor 7-12 Programmable delay 7-13 PCI-Clamp Diode…… LVDS Transmitter Programmable Pre-Emphasis On-Chip Termination Support …17-15 On-Chip termination With Calibration ……….7-15 On-Chip Termination Without Calibration 7-17 I/O Standard 7-20 Termination scheme for I/O Standards 7- Voltage-Referenced l/O Standard Termination Differential I/O Standard Termination 24 I/O Banks......... 726 High-Speed Differential Interfaces 7-31 7-32 Pad Placement and dc guidelines 7-32 Differential Pad Placement Guidelines .......................................................................................7-3 VREF Pad Placement guidelines DC Guidelines 7-37 onclusion Document Revision history ∴7-38 Chapter 8. High-Speed Differential Interfaces in Cyclone Ill Devices Introduction Cⅴ clone ill hi ed I/O Banks . Cyclone Ill High-Speed Altera Corporation Contents I O Interface..... I/O Standards Support……… LVDS IO Standard Support in Cyclone Ill Devices RSDS IO Standard Support in Cyclone Ill Devices ,8-9 mini-LVDSIO Standard Support in Cyclone III Devices.... PPDS IO Standard support in Cyclone Ill Devices LVPECL I/O Support in Cyclone IIT Devices 8-16 Differential Sstl I/O Standard Support in Cyclone Ill Devices Differential HSTL I/O Standard Support in Cyclone Ill Devices Feature of the Dedicated Output Buffer .......8-19 High-Speed imn ng in Cyclone Ill Devices Design Guidelines……………… Differential Pad Placement Guidelines ...............................8-22 Board Design Considerations oftware Overview… Conclusion 8-24 Document revision history 8-24 Chapter 9. External Memory Interfaces in Cyclone I Devices Introduction Cyclone itt memory support overview……、…… 9-3 Cyclone Ill Memory Interfaces Pin Support Data and data Clock/ Strobe Pins Optional Parity, DM, and ECC Pins 9-13 Address and Control/ Command Pins Memory Clock pins……… 9-14 Cyclone Ill Memory Interfaces Features…………… DDR Input Registers……………….….….…..….....9-15 DDR Output Registers………… 9-16 On-Chip Termination(OCT 9-18 PLL 9-18 9-19 Document Revision history 9-19 Section Il Configuration, Hot Socketing Remote Upgrades, and sEU Mitigation Chapter 10. Configuring Cyclone Ill Devices Introduction Configuration Devices .10-2 Configura Configuration File Format 10 Altera Corporation Contents Cyclone Ill Device Handbook, Volume 1 Configuration Features Configuration Data Decompression Remote System Upgrade…… 10-11 Configuration Requirements ·‘···; 10-12 Power-On Reset Circuit .410-12 Configuration and TAG Pin I/O Requirements .....10-13 Active Serial Configuration(Serial Configuration Devices) 10-14 Multi-Device AS Configuration Single device as Configuration ..10-15 Configuring multiple cyclone Ill Devices with the Same design……".∴、…… 10-20 Estimating As Configuration Time 10-26 Programming scrial configuration devices 10-26 Active Parallel Configuration(Supported Flash Memories 10-29 AP Configuration Supported Flash Memories …10-31 Single device ap configuration 10-33 Multi-Device AP Configuration 10-38 Configuring With Multiple Bus masters…… 10-42 Estimating aP Configuration Time 10-43 Programming Parallel Flash Memories……………… 10-44 Passive Serial Configuration ... 1046 PS Configuration Using a MAX II Device as an External Host 1046 PS Configuration Using a Microprocessor PS Configuration Using a Download Cable ∴.410-56 Fast Passive Parallel configuration 10-61 FPP Configuration Using a MAX II Device as an External Host ∴10-62 FPP Configuration Using a microprocessor 10-70 JTAG Configuration 10-70 Jam STAPL 10-78 Configuring Cyclone Ill Devices with rUnner 1079 Combining jTAG and Active Scrial Configuration Schemes 10-79 Cyclone Ill JTAG Instructions ∴410-8 I/ O Reconfiguration……………… 10-81 Overriding the Internal Oscillator……… 10-85 Changing the Start Boot Address of AP Flash 10-86 Device Configuration Pins 10-87 Conclusion Document revision history.…… “ Chapter 11. Hot Socketing and Power-On Reset in Cyclone lll Devices Introduction Cyclone III Hot-Socketing Specifications Devices Can be driven before power-U 11-2 IO Pins Remain Tri-Stated During Power-Up 11-2 Hot-Socketing Feature Implementation in Cyclone Ill Devices On reset circuitr Wake-Up Time for Cyclone III D evices Conclusior Altera corporation

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