iv Altera Corporation
Cyclone II Device Handbook, Volume 1
Contents
Multiplier Modes ............................................................................................................................ 2–35
Embedded Multiplier Routing Interface ..................................................................................... 2–36
I/O Structure & Features .................................................................................................................... 2–37
External Memory Interfacing ....................................................................................................... 2–44
Programmable Drive Strength .....................................................................................................2–49
Open-Drain Output ........................................................................................................................ 2–50
Slew Rate Control ........................................................................................................................... 2–51
Bus Hold .......................................................................................................................................... 2–51
Programmable Pull-Up Resistor .................................................................................................. 2–51
Advanced I/O Standard Support ................................................................................................ 2–52
High-Speed Differential Interfaces ..............................................................................................2–53
Series On-Chip Termination ......................................................................................................... 2–55
I/O Banks ........................................................................................................................................ 2–57
MultiVolt I/O Interface ................................................................................................................. 2–60
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1
Configuration ......................................................................................................................................... 3–5
Operating Modes ................................................................................................................................... 3–5
Configuration Schemes ......................................................................................................................... 3–6
Cyclone II Automated Single Event Upset Detection ...................................................................... 3–7
Custom-Built Circuitry .................................................................................................................... 3–7
Software Interface ............................................................................................................................. 3–7
Document Revision History ................................................................................................................. 3–8
Chapter 4. Hot Socketing & Power-On Reset
Introduction ............................................................................................................................................ 4–1
Cyclone II Hot-Socketing Specifications ............................................................................................ 4–1
Devices Can Be Driven before Power-Up ..................................................................................... 4–2
I/O Pins Remain Tri-Stated during Power-Up ............................................................................ 4–2
Hot-Socketing Feature Implementation in Cyclone II Devices ....................................................... 4–3
Power-On Reset Circuitry .................................................................................................................... 4–5
"Wake-up" Time for Cyclone II Devices ....................................................................................... 4–5
Conclusion .............................................................................................................................................. 4–7
Document Revision History ................................................................................................................. 4–7
Chapter 5. DC Characteristics & Timing Specifications
Operating Conditions ........................................................................................................................... 5–1
Single-Ended I/O Standards .......................................................................................................... 5–5
Differential I/O Standards .............................................................................................................. 5–7
DC Characteristics for Different Pin Types ..................................................................................... 5–11
On-Chip Termination Specifications ........................................................................................... 5–12
Power Consumption ........................................................................................................................... 5–13
Timing Specifications .......................................................................................................................... 5–14
Preliminary & Final Timing Specifications ................................................................................. 5–14
Performance .................................................................................................................................... 5–15
Internal Timing ............................................................................................................................... 5–18
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2010-03-11
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