基于FPGA的数码管显示程序

module shumaguan(clk_50M,duan_ma,wei_ma);
input clk_50M;              //输入时钟
output [7:0] duan_ma;      //数码管的公共段码
output [7:0] wei_ma;       //8位数码管的位选信号
reg [7:0] duan_ma;
reg [7:0] wei_ma;
reg [15:0] count;//分频计数器，65536分频
reg  div_clk=0;

reg [3:0] num1,num2;


//分频计数器
always @ ( posedge clk_50M )
begin
if ( count==65535 )
 begin
  div_clk<=~div_clk;
   count<=0;
  end
else
  count<=count+1;

end

//位选信号，每次只选通一位数码管
always @ ( posedge div_clk )
begin
 case ( num1 )
 0: