ISSI DDR2 128Mx16 data sheet

IS43/46DR16128

Integrated Silicon Solution, Inc. – www.issi.com – 1

Rev. 00B, 3/28/2011

2Gb (x16) DDR2 SDRAM

FEATURES

 Clockfrequencyupto400MHz

 8internalbanksforconcurrentoperation

Sequentialor

 ProgrammableBurstLength:4and8

 AutomaticandControlledPrechargeCommand

 PowerDownMode

 AutoRefreshandSelfRefresh

 RefreshInterval:7.8s(8192cycles/64ms)

 OCD(Off‐ChipDriverImpedanceAdjustment)

 ODT(On‐DieTermination) 

 WeakStrengthData

 DifferentialclockinputsCKandCK#

 VDDandVDDQ=

1.8V±0.1V

 PASR(PartialArraySelfRefresh)

 SSTL_18interface

 tRASlockoutsupported

 Operatingtemperature:

Commercial(T

=‐40°Cto85°C;T

=‐40°Cto95°C)

Automotive,A2(T

=‐40°Cto105°C;T

=‐40°Cto

105°C)

 Configuration:

Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS43/46DR16128

BankAddress

I/O

UpperByteDataStrobe

LowerByteDataStrobe

OnDieTerminationEnable

Noconnect

Symbol

LDQS,LDQS#

VSS

VSSQ

IS43/46DR16128

resultinundefinedoperation.

Power‐upandInitializationSequence

ThefollowingsequenceisrequiredforPower‐upandInitialization.

1. EitheroneofthefollowingsequenceisrequiredforPower‐up:

complete

IS43/46DR16128

IS43/46DR16128

WR

c

cles

7

4

4

6

Yes

DLLReset

5

6

7

BurstType

Address

Field

Mode

1. WR(writerecoveryforautoprecharge)minisdeterminedbytCKmaxandWRmaxisdeterminedbytCKmin.WRinclockcyclesiscal culatedbydividingtWR(in

A1is

usedforenablingreducedstrengthdata‐outputdriver.A3‐A5determinestheadditivelatency,A2andA6areusedforODTvalue

selection,A7‐A9areusedforOCDcontrol,A10isusedforDQS#disableandA11isusedforRDQSenable.