简单AMP:在ZYNQ SoC处理器上运行Linux和裸机系统

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在zynq上双系统搭建的教程,cpu0跑linux,cpu1跑裸程序。
Design Overview R XILINX Hardware The PL contains a custom, embedded core connected to a synchronous output of a Chip Scope analyzer Vio core(Figure 1). The VIo core provides a mechanism for a user to interact with nardware from Chip Scope analyzer ILA VIO Irg_gen Core 1 nIRQ pcore PS AXI Interconnect MAXI GPO X107801011513 Figure 1. PL Block Diagram In this design, when the vio generates a pulse, the custom core forwards an interrupt to the Ps Corel_nIRQ pin. The core is also connected to the Ps master general purpose port (M_AXI GPO)through an AXI Interconnect, allowing both CPU0 and CPU1 access to the control register within the core CPU1 accesses the control register to clear the interrupt request(IRQ)during the interrupt service routine. CPUo can optionally use the control register to create an interrupt towards CPU1. the Core1_nIRQ pin connects directly to CPU1s PPI block so there is no need to modify the configuration of the shared ICD. A Chip Scope analyzer AXI monitor core is also included and allows the user to measure the latency of the IrQ being serviced Address Map In the PL, there is a single irq _gen embedded core that contains a single control register. The register is located at BASE+0(0x78600000). Table 1 contains a description of the IRQ_GEN control register. Table 1: IRQ GEN Control Register Bit Access Description [31:1] R/W Unused, value written can be read IRQ Asserted 0: IRQ is not asserted towards the Ps R/W 1: RQ is asserted towards the ps. if the vio IRQ ticK pin is asserted(by the vIO), this bit is set. Also, the CPU can set this bit. Only the CPu can write this bit to clear it XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Design Overview R XILINX Software The software can be broken down into three sections First stage boot loader(FSBL) Linux operating system and applications for CPUo Bare-metal operating system and application for CPU1 SBL The FSBL always runs on CPUO It is the first software application that is run after power-on reset of the Ps. The FSBL is responsible for programming the PL and both application executable and linkable format (ELF)files to DDR memory. After loading the applications to DDR memory, the FSBL starts executing the first application that was loaded However, the version of FSBL included in the ISE Design Suite 14.3 does not support multiple data or Elf files. The fsbl first looks for a bit file if a bit file is found the fsbl writes it to the PL. Next, whether or not a bit file is found, the FSBL loads one application ELF into memory and executes it. This operating sequence does not support such an AMP configuration, so the FSBL must be modified Within this AMP example's project files, the fsBl has been modified to continue searching for files and loading them into memory until it detects a file that has a load address of OXFFFFFFFO. Upon detection, the FSBl downloads this last file and jumps to the executable address of the first non-bit or non-boot file found ( which is the application for CPUo). For details regarding how CPU1 starts up, refer to Zyng-7000 A// Programmable Soc Technical Reference Manual [Ref 1 Linux The easiest way to use Linux in an AMP configuration is to configure Linux as symmetric multiprocessing(SMP) but restrict the number of available CPUs to 1. Such an approach ensures that Linux configures the ICd and SCU correctly for a multiple CPU environment To create the Linux kernel, U-Boot, device tree, and the root file system ramdisk, refer to the wikipagesathttp:/wiki.xilinx.com.Allgeneratedfilesareavailableaspartoftheprojectfiles accompanying this application note. To instruct Linux to use only one CPU for SMP, the bootargs in the device tree is modified to add maxcpus=1. By default, the Linux. config is already setup to use SMP on the Zc702 demonstration board The device tree is also modified to reduce the amount of memory available to Linux to provide untouched memory space for CPU1's application Linux Applications TWo Linux applications that run on CPUo are provided to interact with CPU1 that is running the bare-metal application. The first application, rwmem, provides a simple memory read and write access from Linux to OCM. This rwmem application is used to peek and poke addresses in OCM. As specific address locations are changed, CPU1 detects the changes and interacts in a specific way. The second application, softUart, provides a UART-style communication between Linux running on CPUO and bare-metal running on CPU1 through predefined memory locations in ocm After the PS powers up and the internal boot ROM completes execution, CPU1 will have been redirected to a small piece of code in OCM at OXFFFFFE00 This piece of code is a continuous loop that waits for an event, checks address location OxFFFFFFFO for a non-zero value and then continues the loop. If OxFFFFFFFC contains a non-zero value, CPU1 will jump to the fetched address XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Design Overview R XILINX CPUo(running Linux)starts CPU1(running bare-metal) by writing the value of 0x30000000 to address OxFFFFFFFO using the included rwmem application. Normally, CPU0 would need to run a set event(sEv) command to wake up CPU1. Because Linux, running on CPUO, is constantly servicing interrupts(another source of events), an SEV command is not necessary When CPU1 wakes up, it reads the value 0x30000000 from address OxFFFFFFFo (written using the rwmem command)and then jumps to address 0x30000000. Note that the FSBL placed CPU1's ELF at 0x30000000 The softUart application, which is also included in the design files, is run as a background task in Linux. When running, softUart continuously monitors shared OCM memory at locations OxFFFF9000(COMM_TX FLAG OFFSETand OxFFFF9004 (COMM TX DATA OFFSET Whenever a 1 is present at CoMM_TX_ FLAG_OFFSET, softUart reads the value found at COMM_TX_DATA_OFFSET and temporarily stores the value in a string array. When a value of OxOA (n) is received, the string array is displayed on STdOUT. Every time softUart reads a value from comm tx data offset. it clears the comm tx flag offset content this clear signals to CPU1 that another character can be sent towards the softUart application running on Linux Bare-Metal Application Code The reference design has CPU1 running bare-metal application code. Linux, running on CPUO, is responsible for initializing shared resources and starting up CPU1 The bare-metal board support package(BSP)named standalone_v3_07_a that is part of the EDK 14.3 install includes support for the preprocessor define constant USE_AMP. This constant prevents the BSP from re-initializing the Ps sCu that has previously been initialized by CPU0. One caveat of using the USE AMP constant is that the MMU mapping is adjusted to create an alias of memory where the physical memory located at address 0x20000000 is virtually mapped to 0x00000000 This remapping is done in the BSP file boot. s. The re-mapping is not necessary for this design a modified version of the bsp is included in the reference design to remove the re-mapping when USE_AMP is set Within this AMP reference design, no Zynq UARTs are used by the bare- metal application Instead, the application running on CPU1 contains its own outbyte function that is used to communicate via OCM to a software UART running in a Linux application on CPUO. By adding the outbyte( function, all stdout functionality of the standalone bsP is intact, allowing functions such as xil_printf to be used To prevent shared resource conflicts, the bare-metal application running on CPU1 must be careful not to access resources such as the scU. linux disables cache access to the ocm However, the default standalone BSP would attempt to enable cache for OCM and therefore conflict with Linux. When used in an AMP configuration, the function XIL_SetT IbAttributeso is used in the CPU1's main( application function to disable cache on OCM. the XIL- SetTlbAttributes( function has been modified in the included source code such that it only flushes L1 cache and leaves l2 cache untouched to prevent access to the scu where L2 cache is controlled If the bare-metal code running on cPu1 requires control of l2 cache, a communications channel must be created allowing the bare-metal code to request Linux to make the necessary changes to the SCU. This action is beyond the scope or requirement for this example design so care has been taken to prevent SCU access directly from the bare- metal code CPU1 Application CPU1's application is located in memory starting at address 0x30000000. The linker script is used to set the starting address CPU1's application does the following 1. Configures the mmu to disable cache for ocm accesses in the address range of OxFFFF0000 to OxFFFFFFFF The address mapping of the oCM is untouched So OCM exists at addresses ox00000000-0x0002Ffff and addresses XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Reference Design R XILINX OXFFFF00OO-OXFFFFFFFE Only the high 64 KB of OCM is used by the design so cache is disabled on addresses OxFFFF0000-OXFFFFFFFF 2. Initializes the PPI interrupt controller and interrupt subsystem 3. Increments an OCM location(COMM_VAL). This OCM location is referred to as the Heartbeat 4. Sleeps for one second 5. CPU1's main( function repeats step 3 and step 4 continuously 6. As interrupts are detected, an interrupt service routine in the background clears the interrupt status of the embedded core and prints a string. The output from the print statement is redirected to use the oCM comm tX flag oFFSet and COMM TX DATA OFFSET locations. In turn, Linux consumes the OCM data and prints the string to the Linux console Reference The reference design files can be downloaded from Design https://secure.xilinx.com/webreg/clickthrough.do?cid=202155 The reference design matrix is shown in Table 2. Table 2: Reference Design Matrix Parameter Description General Developer name John Mcdougall Target devices(stepping level, ES, production, speed XC7Z020-CLG484-1 grades Source code provided Yes Source code format VHDL and Verilog Design uses code/lP from existing Xilinx application note/reference designs, CORE Generator software,or third party Simulation Functional simulation performed No Timing simulation performed Test bench used for functional and timing simulations No Test bench format N/A Simulator software/version used NA SPICE/IBIS simulations No Implementation Synthesis software tools/version used XST 14.3 Implementation software tools/versions used EDK 14.3 Static timing analysis performed Yes Hardware verification Hardware verified Yes Hardware platform used for verification ZC702 board XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com 6 Implementation Details R XILINX The reference design contains these files · XPS project SDK source files for Linux and CPU1 applications Generated files including Bit file All files for the sd card Application ELF files for Linux and CPU1 B○oT. BIN build scripts Modified bare- metal bsP Modified sw_apps FSBL Modified devicetree ats and devicetree. ath Table 3 and Table 4 show the device utilization details Table 3: Device Utilization (1) Parameters Specification/Details Device utilization without testbench Slices 246 GclK buffers 2 PS7 RAMB36 HDL language support erilog/hdl Table 4: Device Utilization(2) Device Speed Grade Package/ Pre-Map(synhesIs Constraint) Post-Route Slices XC7Z020 1 CLG484 240 MHZ 160 MHZ 246(1%) mplementation This section discusses the implementation of the reference design Details The design files should be extracted to a directory called des ign. After the files have been extracted, a new directory called design \work should be created Files should be copied as shown design\src\bootgen to design\work\bootgen design\src\eak system to design\work\edk_ system All generated files have been included and are located in the directory designgenerated files Generating hardware This section describes the creation of the hardware design. The user can skip this section and go to Generating Applications. The pre-compiled design is available at design generated files\ fpga download. bit To implement the embedded design and export it to sdK 1. Start XPS and open the embedded project at design\work\eak_system\ system. xmp XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Implementation Details R XILINX 2. Select device_configuration >update_bitstream. After it completes, the downloadable FPGa bit file is available at design\workeak_system\implementation\ download. bit a precompiled version of the bit file is also available at design\ generated files\ fpga\download. bit 3. Export the hardware project to SDK by selecting project export_hardware_design_to_SDK. Check the Export Launch sDK button. At this point, XPS exports the embedded system configuration via a system. xml file that is used by sdK to understand what peripherals are present in the design and what the base addresses are. the file is automatically exported to design\work\eak_system\ SDK\SDKExport\hw SDK opens a dialog box asking where the workspace is located. Browse to and select the directory design\work\eak_system\ SDK, click OK Before clicking OK a second time, add to the end of the selection \Workspace as shown in Figure 2. SDK automatically creates the Workspace subdirectory Workspace launcher Select a workspace Xilinx SDk stores your projects n a folder called a wnrcspart Choose a workspace folder to use for this session Workspace:C:\design\work\edk_system\ SDK\Workspace Br r。wvse s Copy Settings OK X107802011713 Figure 2: Select Workspace Directory Generating Applications Configuring SDK The standalone BSP files(used by the bare-metal application) and modified FSBl files have been included in this design To give SDK knowledge of these files, SDK needs to be configured to have knowledge of the new repository Start SDK and open the workspace at design\work\eak_system\SDK\ Workspace This step is not necessary if XPS was used with Export Launch SDK 2. Point sdK to the included repository that contains the modified standalone bsp and modified FSBL(Figure 3) Select Xilinx_ tools repositories Select New for local repositories Browse to and select the directory design\src\sak_repo Select OK XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Implementation Details R XILINX yr References I typefiter text Add, remove or change the order of sDks software repositories General Local Repositories(available to the current workspace C/C++ Hep C\design\src\ sdk_rep N∈wn remote Systems Fun/ Debu Xilinx sDo Boot im Relati Flash Programming Global Repositories (availab e across work e Hardware Specification Log lnformation Level New Repositories Torget Manage Remove XMD Startup SDK Installation Repositories C\Ailnx1431143VSE_US\ELK,w/lib\ C\Ailnx 14.3 14, sE DSEDK sw nocessorlPLib CVil 14,3143\ISE DS\EDK sw\ ThirdParty escan Repo Note: Local repository settings take precedence over global repository settings. Restore defar Apply OK X107803011 Figure 3: Select Repository XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com Implementation Details R XILINX Creating Custom FSBL Application 1. Ensure that the Configure SDK section has already been run 2. Create the FSBL using the new template from the repository (Figure 4) a. Select File >New>Application_Project b. Set the project name to amp_ fsb New project Application Proje Create a managed make applieation project. 回 Use default location cn×+143m43 ked sy Browse.,」 hoose file syste sy default Target Hardware Hardware Platform edk_system_hw_platform Processor 57 cortexes Q Target Software as Platform Standalone Larguage OC C Board Support Package Create New amp_fshl_hsn o Use existing Back Next> Finish Cancel X1078040117 Figure 4: Create FsBL c. Click Next XAPP1078(v1. 0) February 14, 2013 NWw.xILinx. com 10

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试读 34P 简单AMP:在ZYNQ SoC处理器上运行Linux和裸机系统
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    asbhunan129 xilinx官网的xapp1078教程,对编程没有帮助,不要下载。
    2018-08-28
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